Jasper Design Automation | Jasper Verification with ARM

View the Cache Coherency and Verification Seminar presented by ARM and Jasper

If you missed DAC, then you missed the seminar on cache coherency and verification of cache coherency given by ARM and Jasper. We have made this seminar available to you on-line. Click below to register and view the seminar.

Abstract: The implementation of hardware-based coherency in high-performance parallel compute environments is not new. However, architects and designers of high-performance, heterogeneous, embedded multi-processing SoC’s, particularly those with one or more caches and when many masters share a single area of memory, now require robust specifications, design & verification tools and systems IP, to ensure their devices minimize off-chip memory transactions, while maximizing performance and power efficiency. This presentation will explore why ARM has chosen to include Coherency Extensions within the AMBA4 specification and will walk the audience through an example cache coherent compute sub-system.

While this is a tremendous benefit, questions of how cache coherency is verified are raised. Jasper has worked closely with ARM to rigorously validate the protocol using Jasper’s unique formal technology. The seminar will share the work that was done by Jasper and ARM to validate the ACE specification and allow ARM to deliver the protocol specifications with high confidence. The seminar will also show how ARM licensees can use the verification IP and methodology that was used at ARM in the verification of their own SOC.