Post-Silicon Debug

Post-silicon debug is painful and slow. Observability into silicon is very limited and is expensive to achieve. Simulation and emulation is slow and is extremely tough to hit corner-case scenarios, concurrent and cycle-dependent behavior. With simulation, the hope is that the constrained-random generator will hit the input combination, which caused the failure scenario (triggered the bug). Not the least, time-to-market is a major concern when complex post-silicon bugs surface, and it takes time to find the root cause and the fix of the issue.

The Jasper Post-Silicon Debug solution

  • Accelerates root-cause isolation by quickly eliminating false areas and narrowing down the problematic area
  • Interactive analysis and debug with The Jasper VisualizeTM technology aids in quickly finding the counter-example (failure of a property) and modifying the traces to confirm/rule-out suspects
  • Mathematically finds the failure scenario starting from extracted failure trace
  • Rapidly isolates and fixes the bug by searching deep into the state-space in areas where simulation cannot reach
  • Validates the fix using Jasper’s powerful proof engines to ensure that no new bugs are introduced


Learn more about the JasperGold Formal Property Verification App for addressing formal property verification issues.