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Formal Verification Unleashed Jasper Design Automation Jasper Design Automation Contact Details Jasper Company Overview Jasper’s Formal Expert Support Jasper Design Automation's Customers Jasper-Formal Verification News and Events Jasper Design Automation Formal Verification Solutions Portfolio
Jasper Design Automation Contact Details Jasper Company Overview Jasper’s Formal Expert Support Jasper Design Automation's Customers Jasper-Formal Verification News and Events Jasper Design Automation Formal Verification Solutions Portfolio
 
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Advanced EDA technology is a crucial link to the next generation of SoC design.

At Jasper, we're committed to ongoing innovation in formal technology. This commitment has been a core component of our ability to deliver high-value solutions to our customers. One reflection of this investment has been our growing portfolio of patents.

To date, Jasper has been issued fourteen patents by the U.S. Patent and Trademark Office and has 4 other patents pending.

Number Title
Issued
6611947 Method For Determining The Functional Equivalence Between Two Circuit Models In A Distributed Computing Environment
08/26/03
6993730 Method For Rapidly Determining The Functional Equivalence Between Two Circuit Models
01/31/06
7020856 Method For Verifying Properties Of A Circuit Model
03/28/06
7065726 System And Method For Guiding And Optimizing Formal Verification For A Circuit Design
06/20/06
7137078 Trace Based Method For Design Navigation
11/14/06
7159198 System And Method For Identifying Design Efficiency And Effectiveness Parameters For Verifying Properties Of A Circuit Model 01/02/07
7237208 Managing Formal Verification Complexity Of Designs With Datapaths 06/26/07
7412674 System and method for measuring progress for formal verification of a design using analysis region
08/12/08
7418678 Managing Formal Verification Complexity of Designs with Counters
08/26/08
7421668 Meaningful visualization of properties independent of a circuit design
09/02/08
7437694 System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design
10/14/08
7506288 Interactive Analysis and Debugging of a Circuit Design During Functional Verification of the Circuit Design
04/17/09
7647572 Managing Formal Verification Complexity Of Designs With Multiple Related Counters
1/12,/10
7895552 Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction 
22/02/11
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