Jasper Intellectual Property

Advanced EDA technology is a crucial link to the next generation of SoC design.

At Jasper, we're committed to ongoing innovation in formal technology. This commitment has been a core component of our ability to deliver high-value solutions to our customers. One reflection of this investment has been our growing portfolio of patents.

To date, Jasper has been issued 23 patents by the U.S. Patent and Trademark Office and has many other patents pending.

Number Title
6611947 Method for Determining the Functional Equivalence Between Two Circuit Models in a Distributed Computing Environment
6993730 Method for Rapidly Determining the Functional Equivalence Between Two Circuit Models
7020856 Method for Verifying Properties of a Circuit Model
7065726 System And Method for Guiding and Optimizing Formal Verification for a Circuit Design
7137078 Trace Based Method for Design Navigation
7159198 System And Method for Identifying Design Efficiency and Effectiveness Parameters for Verifying Properties of a Circuit Model
7237208 Managing Formal Verification Complexity of Designs With Datapaths
7412674 System and Method for Measuring Progress for Formal Verification of a Design Using Analysis Region
7418678 Managing Formal Verification Complexity of Designs with Counters
7421668 Meaningful Visualization of Properties Independent of a Circuit Design
7437694 System and Method for Determining and Identifying Signals that Are Relevantly Determined by a Selected Signal in a Circuit Design
7506288 Interactive Analysis and Debugging of a Circuit Design During Functional Verification of the Circuit Design
7647572 Managing Formal Verification Complexity Of Designs With Multiple Related Counters
7895552 Extracting, Visualizing, and Acting on Inconsistencies Between a Circuit Design and Its Abstraction 
8103999 Debugging of Counterexamples in Formal Verification
8205187 Generalizing and Inferring Behaviors of Circuit Design
8225249 Static Formal Verification of a Circuit Design Using Properties Defined with Local Variables
8381148 Formal Verification of Deadlock Property
8516421 Generating Circuit Design Properties from Signal Traces
8527911 Comprehending a Circuit Design
8572527 Generating Properties for Circuit Designs
8630824 Comprehending Waveforms of a Circuit Design
8671373 Analysis of Circuit Designs Via Trace Signatures