IN THE NEWS

Jasper Design Automation's Kathryn Kranen Moderates DAC Pavilion Panel on Today's Consumer at the 45th Annual Design Automation Conference

What Makes Current Products Cool and What Will be Needed in the Future

Mountain View, Calif. – April 23, 2008 – Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced that president and CEO, Kathryn Kranen, will moderate a unique panel on today’s consumers.

Jasper Design Automation Adds Tom Melham And Moshe Vardi To Its Technical Advisory Board

Verification Industry Visionaries Contribute To Jasper's Formal Technology Development

Mountain View, Calif. – April 22, 2008 – Jasper Design Automation, the leader in successful deployment of production-proven formal verification solutions, today named Tom Melham and Moshe Vardi as the newest members of its Technical Advisory Board (TAB). Tom Melham is a Professor of Computer Science at the University of Oxford and a Fellow of Balliol College. He is well-known for his technical contributions and publications on combined model checking and theorem proving, industrial-scale hardware verification, abstraction techniques, and for integrating formal verification into hardware design methodologies. Moshe Vardi is a Professor of Computer Science at Rice University, the Karen Ostrum George Professor in Computational Engineering, and Director of the Ken Kennedy Institute for Information Technology. The author of over 300 technical papers, as well as the editor of several collections, Prof. Vardi is a renowned expert in model checking, constraint satisfaction and database theory, common knowledge (logic), and theoretical computer science.

Jasper Design Automation Unveils Its Production Proven Proof Accelerators For Rapid and Exhaustive Verification of Intractable Datapath Designs

Delivering Orders of Magnitude Greater Coverage than Simulation alone, JasperGold® Verification System Modeling Extensions Reduce Complexity, Improve Performance and Dramatically Increase Formal Capacity

Mountain View, Calif. – April 9, 2008 – Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today unveiled a powerful set of modeling extensions – Formal Scoreboard™ Proof Accelerator, Clock Domain Crossing (CDC) Proof Accelerator, Cache Proof Accelerator and FIFO Proof Accelerator – for the rapid and exhaustive verification of intractable datapath designs. Delivering orders of magnitude greater coverage than traditional simulation alone, the unique JasperGold® Verification System Proof Accelerators reduce complexity, improve performance and dramatically increase formal capacity. While used successfully on production computing, consumer electronics, networking, and microprocessor chips, JasperGold’s Proof Accelerators can also be used to accelerate the functional verification of any complex chip where datapath, multiple clock domains, caches and FIFOs pose a verification challenge.

Jasper Design Automation Joins The SPIRIT Consortium to Champion Structured Verification Planning

Jasper will Focus on the Exchange of Verification Plan Data via XML

Mountain View, Calif. – Dec 5, 2007 – Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced it has become a Reviewing member of The SPIRIT Consortium, a standards organization focused on IP/tool integration and laying the foundation for design flow integration. The Consortium has made great strides with its IP-XACT™ format, an Extensible Markup Language (XML) Schema for meta-data documenting Intellectual Property (IP) used in the development, implementation and verification of electronic systems. Jasper Design Automation has also used XML in the development of its GamePlan™ Verification Planner, a widely-adopted free tool for enabling structured verification planning. As a member of The SPIRIT Consortium, Jasper intends to champion development of a standard data set, using a format based on XML, for support of structured verification planning industry-wide, regardless of the chosen tool flow.

Jasper Design Automation Hires Distinguished Formal Verification Expert Ziyad Hanna as Chief Architect and Vice President of Research

Prominent Intel Veteran Will Drive Formal Technology Research For Greater Design and Verification Productivity

Mountain View, Calif. – Dec 5, 2007 – Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced it has hired prominent formal verification expert, Ziyad Hanna, to serve as chief architect and vice president of research. Prior to joining Jasper, Hanna was Intel senior principal engineer and the main leader of the Formal Technology Research and Development Group in the Design and Technology Solutions division at Intel Haifa. At Jasper, Hanna will work alongside Claudionor Coelho, vice president of engineering, and Rajeev Ranjan, chief technology officer, to further advance the company's breakthrough formal verification technology. These widely-respected technologists will lead a shared engineering team that will rotate between research and productization phases to deliver a pipeline of formal verification advances that are productized quickly and made available in production form to Jasper's customers.

Jasper Design Automation Releases GamePlan™ Verification Planner v1.2 Enabling Tracking of Verification Results within Dynamic Verification Plans

Free Verification Planning Tool Delivers Verification Progress Tracking, Improved Search Capabilities and Easy Organization

Mountain View, Calif. – Oct 3, 2007 – Further enhancing its free solution that addresses one of the key problems facing verification teams, Jasper Design Automation today announced availability of GamePlan™ Verification Planner version 1.2, a powerful tool for generating and tracking verification plans. In version 1.2, GamePlan now includes the ability to import verification results. After an easy set-up that takes no more than a couple of hours, verification teams can begin reading verification results back into their test plan to efficiently track their verification progress. In addition, GamePlan also delivers improved search capabilities, active hyperlinks in analysis views for easy organization, and a new Undo/Redo feature for improved usability.

Jasper Design Automation Announces JasperGold® Verification System v4.5 Featuring Liveness Property Support, Improved Modeling and Faster Engine Performance

Latest Release Improves Initialization Performance, Delivers Better Push-Button Mode Completion Rates and Provides Automatic Property Grouping for Faster Proofs

Mountain View, Calif. – Oct 3, 2007 – Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced JasperGold® Verification System v4.5, a new release of the company's flagship formal verification solution that delivers support for liveness properties, enhanced engine performance and support for properties containing multiple clocks - a new functionality important for modeling the industry's most sophisticated properties. In release 4.5, JasperGold also includes improved initialization performance for easier formal analysis and automatic property grouping for faster proofs.