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Publication Articles
2007
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May 10 Verifying Configurable Verification Interfaces Using OCP (EE Times)
Feb 27 Formal Verification Takes To "Sandbox" (Electronic Design)
2006
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Dec 14 Accellera seeks verification coverage standard (EE Times)
Jul 19 Latest Jasper release touts better user experience (EE Times)
Jul 10 Formal verification: where to use it and why (EE Times)
Feb 08 Panelist seek ROI in IC verification (EE Times)
2005
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Oct 03 Verification experts put formal in its place (EE Times)
May 25 Jasper releases new version of flagship verification product (EE Times)
May 23 Formal approach offers verification 'salvation' (EE Times)
Jan 12

Jasper acquires formal tool vendor Safelogic

 (EEDesign)
2004
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Dec 17 The hot 100 products of 2004 (EDN)
Jul 09 Who’s Driving the Design Chain? (Electronic News)
May 25 Tool provides hierarchical verification (EDN)
May 24 Formal Verification Moves Into Design Phase (Electronic Design, Tech View)
May 03 Jasper Design Automation Pioneers
Provably Correct Design Methodology		 (SOCcentral.com)
May 03 Jasper upgrades verification product (EE Times)
Apr 20 EDA Consortium elects new board members (EE Times)
Feb 27 EDA CEOs predict growth, cite cost concerns (EE Times)
2003
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Oct 20 EDA vendors tip plans for SystemVerilog (EE Times)
Sep 08 The Natural (Silicon Valley / San Jose  Business Journal)
Aug 04 A Delicate Balance ::
Which are the factors that tip the scales?		 (EDA Cafe)
Jun 09 Formal Tool Smashes Through Capacity Barrier (Electronic Design, Tech View)
May 30 Synopsys rival emerges from stealth mode (Silicon Valley Business Ink)
May 19 Startup promises 'pure' formal tool for verification (EE Times)
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