Why you should attend:
This panel will speak to critical issues in verification that consume the time, resources and energies of companies around the globe. While a design is being verified, the verification teams must know if their efforts are progressing according to the schedule. To be able to declare when verification is “done”, teams need to effectively assess the risk of bug escapes. Often, these teams use a verification coverage plan to help them address these issues. However, increasing complexity and IP integration place growing demands upon verification teams. Our panelists, a group of respected functional verification experts and innovative solution suppliers, will examine, compare and debate the various aspects of what it takes to build an effective verification plan for today’s increasingly complex electronic devices.

Previously, verification plans described the scenarios under which a device needed to be tested. With the changes imposed by new and evolving technologies (i.e. formal verification, emulation and acceleration), these same plans have needed to expand and evolve to adapt.

At the core of functional verification lies coverage, and it is a topic of considerable discussion and debate. This panel will strive to address the following set of questions:
• What are the various coverage metrics in used today, and do these metrics correctly address the functional verification burden?
• How do you begin to integrate multiple verification processes into a single test plan?

With the tremendous rise in chip complexity and IP integration, companies are beginning verification at higher levels of abstraction to better understand the overall system functionality. Industry-leading companies have already embraced the use of formal verification, emulation and acceleration to drive greater functional verification success in their push for higher quality and greater schedule predictability.
• What value do these new verification processes bring, and what usage and integration burden do they pose?

It is no longer just a verification plan discussion, but an examination of how verification plans must adapt to new and evolving technologies.

If you would like to learn more about effective verification planning using GamePlan™, or how to successfully integrate formal into your verification flow while at the DATE conference, then please visit stand # M33 to speak with the experts at Jasper Design Automation.

BIOS:

Andrew Piziali is an industry veteran design verification engineer with 23 years experience verifying mainframes, supercomputers and microprocessors with StorageTek, Amdahl, Evans and Sutherland, Convex Computer, Cyrix, Texas Instruments, Transmeta, Verisity and Cadence. Having an avid interest in coverage-driven verification, in 2004 he authored the book Functional Verification Coverage Measurement and Analysis. His new book, co-authored with Grant Martin and Brian Bailey, ESL Design and Verification, was published this spring. Andrew is now chairman of the IEEE 1647 e language working group and an independent consultant.


Craig Deaton holds the position of Senior Methodologist at Jasper Design Automation. He was the key architect behind Jasper's freely available GamePlan™ Verification Planner, and is a strong advocate of verification planning in the global verification community. From 1993 until 2005, Mr. Deaton held positions of increasing verification responsibility at Texas Instruments. In his role as an ASIC verification engineer, he served on TI-wide methodology teams and was a key reviewer of new vendors / tools. He also served as the formal verification leader for TI Wireless in Dallas and consulted with major EDA vendors on technical decisions affecting their product roadmaps. Mr. Deaton has presented papers and served on expert panels at professional forums and is a founding-member company contributor to the Coverage Interoperability Forum (CIF). He received his BSEE from the University of Arkansas.

Mike Benjamin manages the 'IP&Design, Functional Verification Group' at STMicroelectronics. He has over 25 years experience in the design and verification of computer systems. For the last twelve years he has worked for ST on the functional verification of microprocessors and SoCs. His team provide central verification services and help drive the development of methodologies and tools both internally and through research initiatives, standards bodies and partnerships with the EDA industry. He has an MA in Electrical Sciences from the Cambridge University and an MSc in Computation from Oxford.

Avi Ziv is a member of the Verification Solutions and Machine Learning group at the IBM Haifa Research Laboratory, where I lead the verification solution activities of the group. Since joining IBM in 1996, I am working on different topics of simulations-based functional verification. My current work is focused on the areas of functional coverage and coverage directed generation (CDG). I also teach a course at the Technion – Israel Institute of Technology on the subject of simulation-based functional verification. I am a graduate of the Technion – Israel Institute of Technology (B.Sc. in Computer Engineering) and Stanford University (M.Sc. and Ph.D in Electrical Engineering).

Jani Lemberg:
Jani Lemberg is the Verification Technology Manager at Nokia. He is responsible for Nokia's ASIC design verification tool and methodology development. He has more than ten years of experience in ASIC technology having worked for Nokia, Mentor Graphics, and Intel over the course of his career. He received his BSc degree at EVTEK in Espoo, Finland.