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| Press Releases |
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| Jasper Design Automation Verifies
Increasingly Complex SoCs With Growing Portfolio Of Innovative
Formal Technology Patents |
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| Jasper Invests Heavily
In Advancement of Formal Technology; U.S. Patent And Trademark
Office Grants Seven Patents |
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| Mountain
View, Calif., - May 5, 2008: Jasper Design Automation,
provider of advanced formal verification solutions,
today announced a growing portfolio of innovative formal
technology patents to help its worldwide customer base
manage dramatically increasing SoC design complexity.
The company is investing heavily in formal technology
research and development (R&D). As a result of its
aggressive and innovative R&D efforts, Jasper was
granted its seventh patent by the U.S. Patent and Trademark
Office.
Jasper's strong portfolio of patents include the following:
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- Patent 7237208,
Managing Formal Verification Complexity Of Designs
With Datapaths, is instrumental in fast, high level
proofs with data transport end to end properties.
It creates a unique benefit for JasperGold, unparalled
proof convergence, and is also used in JasperGold
Proof Accelerators. This approach has been used and
tuned in cooperation with multiple customers already.
- Patent 7020856, Method For Verifying
Properties Of A Circuit Model, covers advanced design
space tunneling algorithm aspects. It covers a proprietary,
systematic process for formal to reach proof convergence
for complex designs, and allows white box discovery
of design elements, such as datapath elements. This
provides the foundation for Jasper's convergence on
demanding proofs.
- Patent 7065726, System And Method
For Guiding And Optimizing Formal Verification For
A Circuit Design. This second design state tunneling
patent covers additional technologies and applications,
focusing on user interface aspects. The advanced debugging
GUI aspect contributes to Jaspers industry leadership
in deploying design space tunneling with debugging
in the field.
- Patent 7137078, Trace Based Method
For Design Navigation, allows white box debugging,
filtering large amounts of design information to pinpoint
the root cause of design errors, and tracing the root
cause to the specific line of RTL. Jasper's intuitive
user interface and trace generation for debug has
been tuned for formal verification since 2003.
- Patent 7159198, System And Method
For Identifying Design Efficiency And Effectiveness
Parameters For Verifying Properties Of A Circuit Model,
covers a seminal form of formal prediction as well
a form of on-the-fly formal prediction during the
design tunneling process. The concept is the basis
of the Jasper formal predictor.
- Patent 6611947, Method For Determining
The Functional Equivalence Between Two Circuit Models
In A Distributed Computing Environment, and Patent
6993730, Method For Rapidly Determining The Functional
Equivalence Between Two Circuit Models, cover verification
as manifested in equivalence checking.
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The patents that have been
issued to date have enabled Jasper's customers to tackle
highly complex designs without the usual capacity or performance
constraints once associated with formal verification;
to reach proof convergence for complex designs with large
sequential depth due to counters and datapath elements;
and to conduct early formal prediction with unique design
space tunneling technology.
"At Jasper, we have been working aggressively to
address the next generation of SoC design challenges -
from the architecture level down to first silicon - by
innovating and applying advanced formal technologies to
solve key problems at every stage of the design flow,"
said Rajeev Ranjan, Jasper's chief technology officer.
"Our commitment to the advancement of formal technology
has made it possible for us to amass a growing portfolio
of issued and pending patents. Customers applying our
Formal Technology Unleashed tell us that they can now
ensure higher design quality and greater design confidence."
To learn more about Jasper and its Formal Technology Unleashed™
- an advanced verification methodology supported by patented,
best-in-class formal verification solutions to comprehensively
verify complex designs at any stage in the design flow,
from architecture to first silicon - please visit Jasper's
booth #2346 at the 45th annual Design Automation Conference
(DAC) in Anaheim, California, June 8th to the 12th, 2008.
Please visit www.jasper-da.com, call +1.650.966.0200 or
email info@jasper-da.com
for further details.
About Jasper Design
Automation
Jasper Design Automation's production proven formal verification
solutions are used by logic designers, verification engineers
and silicon bring-up teams to design, explore and debug
RTL, to ensure correctness of block-level functionality
and for rapid post-silicon validation and debug. JasperGold®
Verification System delivers complete "deep formal"
systematic verification, ensuring correctness of critical
design features without any testbench development. JasperGold
Express, a "light formal" solution, complements
simulation by accelerating bug-hunting and coverage attainment.
For expert help with large scale formal verification deployment,
RTL exploration or post-silicon debug, please visit http://www.jasper-da.com.
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| Jasper Design Automation,
the Jasper Design Automation logo, JasperGold, Formal
Testplanner, GamePlan, Proof Accelerators, Lossless Abstractions,
Formal Scoreboard, and Design Tunneling are trademarks
or registered trademarks of Jasper Design Automation,
Inc. All other names mentioned are trademarks, registered
trademarks, or service marks of their respective companies.
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