| Mountain View, Calif. –
December 5, 2007 – Jasper Design Automation, the
leader in successful deployment of production proven formal
verification solutions, today announced it has become
a Reviewing member of The SPIRIT Consortium, a standards
organization focused on IP/tool integration and laying
the foundation for design flow integration. The Consortium
has made great strides with its IP-XACT™ format,
an Extensible Markup Language (XML) Schema for meta-data
documenting Intellectual Property (IP) used in the development,
implementation and verification of electronic systems.
Jasper Design Automation has also used XML in the development
of its GamePlan™ Verification Planner, a widely-adopted
free tool for enabling structured verification planning.
As a member of The SPIRIT Consortium, Jasper intends to
champion development of a standard data set, using a format
based on XML, for support of structured verification planning
industry-wide, regardless of the chosen tool flow.
Jasper responded to the industry’s burgeoning
need for structured verification planning in June of
2006 with its introduction of GamePlan Verification
Planner. GamePlan is a powerful free tool used for generating
and tracking verification plans that support multiple
verification technologies. Available for download on
the Jasper website, GamePlan stores the verification
plan data and tracked results in an open XML format
to allow users to easily extract custom data sets for
analysis.
“Since Jasper’s GamePlan also uses an XML
format to enable users to exchange design verification
planning data, we saw the potential for great synergy
with The SPIRIT Consortium,” stated Rajeev Ranjan,
chief technology office at Jasper Design Automation.
“GamePlan has seen an increasing volume of downloads
and very positive responses from users since its launch.
As we participate in The SPIRIT Consortium, we will
be able to share our understanding of the data set supporting
verification planning, regardless of the verification
methodologies employed.”
“Verification is a major source of pain and effort
both for IP components and SoC development, said Ralph
von Vignau, president of The SPIRIT Consortium. “The
industry needs improvements, and it is through companies
like Jasper, that are willing to partake in The SPIRIT
Consortium by reviewing and feeding back ideas and improvements,
that will we be able to ensure the supporting standards
are adopted by the industry,"
About The SPIRIT Consortium
The SPIRIT Consortium is a global organization focused
on establishing multi-faceted IP/tool integration standards
that drive sustainable growth in electronic design.
It is comprised of leading EDA, IP, system integration,
and semiconductor companies dedicated to the adoption
of a unified set of specifications for configuring,
integrating, and verifying IP in advanced SoC design
tool sets. For more information on The SPIRIT Consortium
and its goals, please visit www.spiritconsortium.org.
About GamePlan™ Verification Planner
GamePlan Verification Planner promotes collaboration
within multiple verification teams by providing a single,
comprehensive structured framework for identifying what
design features need to be tested, what verification
technologies are required for testing, and for prioritizing
and tracking the progress of each feature tested. GamePlan
Verification Planner fills the gaps in today’s
verification flow by adding a process for systematic
verification that can fit into any environment, and
that respects all verification methods, including formal
verification, simulation and others. By providing GamePlan
as a free tool, Jasper Design Automation is enabling
systematic use of formal verification alongside other
technologies, and is taking a leading industry role
in promoting a structured approach to verification.
For details visit: http://www.jasper-da.com/gameplan.
About Jasper Design Automation
Jasper Design Automation, a privately-held Electronic
Design Automation (EDA) company with a mission of making
full formal IC verification a competitive advantage
for its customers, is the leader in successful deployment
of formal solutions in production verification environments.
The company’s flagship product, JasperGold Verification
System, is the first verification product to deliver
complete “deep formal” systematic verification,
ensuring correctness where it matters most. JasperGold
formally verifies that complex IC design blocks meet
high-level requirements defined in their specifications,
and also pre-verifies IP blocks for use under all use
modes, without any testbench development. JasperGold
Express, Jasper’s formal ABV solution, provides
the industry’s leading “light formal”
solution, complementing simulation-based approaches
by accelerating bug hunting as well as coverage attainment.
The JasperGold family quickly isolates bugs with a fast,
static debugging capability, and then proves the absence
of bugs, trimming design schedules. For further details
on how to ensure guaranteed correctness where it matters
most, please visit http://www.jasper-da.com.
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