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MOUNTAIN VIEW, Calif. – January 14, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, is introducing the latest release of its JasperGold/JasperCore formal verification system at Yokohama, Japan’s ESDF 2010 beginning Jan. 28. This JasperGold/JasperCore release delivers unprecedented deep proofs and bug-hunting, while adding value across the entire spectrum of formal verification design applications, from architectural and RTL verification to post-silicon debug.
“These new features are highly valued by our customers,” said Dr. Claudionor Coelho, Jasper Vice President of Engineering. “Everything described here has been validated in extensive field trials with some of the world’s most advanced design teams, and greatly accelerates both the science and practical implementation of formal.”
Powerful Proof, Exploration and Productivity Boosters
The new release has been tested with leading IC design teams at major microprocessor, graphics processor, IP, and telecom/networking companies with outstanding results. A sampling of their comments:
- ”Easily handles unit-sized blocks, very impressive tool”
- ”Reads full cores and even multi-core designs”
A new collaborative engine architecture automatically leverages information between engines to boost performance and obtain convergence on complex proofs. Other engines have increased JasperGold/JasperCore’s industry-leading capacity to handle even larger designs, and increase convergence on liveness properties.
JasperGold now features a design explorer dialog where you can access a tree structure of the design logic starting from signals or properties. Design exploration facilitates greater understanding of the design structure and provides an interface to quickly construct the analysis region thus enabling a smooth transition to Jasper’s unique Design Tunneling™ feature for the proof of the most complex properties.
Multi-cycle path analysis applies formal to the general static timing analysis (STA) issue. STA generates voluminous multi-cycle paths, and this JasperGold formal feature clearly identifies which of them will cause problems.
JasperGold formal allows engineers to derive the benefits of X states without the associated risks. The use of unknown values (X states) can provide significant benefits in RTL verification, and can allow better logic optimization for synthesis. Sources of X include direct X-assignment and uninitialized logic. But uncontrolled or unexpected X propagation in simulation can also mask bugs, potentially leading to failures in silicon. Simulation alone cannot adequately simulate and observe all X states.
The typical design methodology calls for appropriate control logic that prevents X propagation past "barrier" points. This flow detects Xs and displays a trace demonstrating the effect of their propagation on user-defined target signals. JasperGold detects functional errors not easily found in simulation, including incorrect clock-gating resulting in Xs for register values and incorrect control logic allowing Xs to propagate to output data buses for “valid” data.
A new path sensitization analysis feature allows engineers to analyze the relationships between various signals, including cause and effect between their activities. In today’s complex designs, it is often difficult to understand how signals interact with each other; e.g., an input potentially affecting the value of the output. JasperGold now detects if a signal can actually affect the value of another signal in the design and displays such a trace if it can be found.
Another JasperGold first is the addition of automatic memory abstraction in the Visualize™ flow, for even greater performance. Visualize automatically generates and manipulates waveforms without a testbench, answering “what-if” design questions and providing visual confirmation of design functionality which is especially useful for RTL development and debug.
Jasper at EDSF 2010
These new products are being featured during EDSF 2010 at the CyberTec/Jasper Booth #304. For more information, or to register for a product demo, please e-mail info@jasper-da.com.
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market. |
