|
DATELINE: From Jasper Design Automation – Mountain View, Calif. – Nov. 17, 2009
EVENT DATES: Dec. 1-3, 2009, Grenoble, France
WHAT
Kathryn Kranen, President and CEO, Jasper Design Automation, will be an invited speaker at this year’s IP-ESC 2009 and appear on two panels. Click on hyperlinks for details.
Speech: High Level Modeling and Verification for IP-Based Systems
Panels: IP Reuse vs. IP Leverage, and Improving IP Quality vs. Losing Design Productivity
WHEN
Tuesday Dec. 1, 2009 (both panels)
11am: IP Reuse vs. IP Leverage: What's the Difference, and What Are the Issues?
5:15pm: Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?
Thursday, Dec. 3, 2009 (invited speaker)
9:30am: High Level Modeling and Verification for IP-Based Systems
WHERE
World Trade Center, Grenoble, France
WHY
IP-ESC 2009 (IP-Embedded Systems Conference) addresses hot topics in the design world, including IP-based SoC design and a continuous technical spectrum from IP to SoC to Embedded System.
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Visit www.jasper-da.com |
