Please register today for the upcoming 2-3 day Jasper Users Group Meeting being held at the Network Meeting Center in Santa Clara, California, on November 5-7th, 2008.

Note that registrations for the tutorial day on Wednesday, November 5th are now closed.

Dates:
Wednesday, November 5th, 9:30am-5:00pm, Opt-In Advanced Hands-On Tutorial - Registrations closed
Thursday, November 6th, 9:15am-5:30pm, Jasper Users Group Seminar Day 1
Friday, November 7th, 9:15am-5:00pm, Jasper Users Group Seminar Day 2

Tutorial Session - Wednesday, November 5th, 2008:

• 9:30 -Continental Breakfast-
• 9:45 Proof Accelerators - New Memory Model
• 10:30 State-space Tunneling
• 11:15 Parallelizing Tasks
• 12:00 -Lunch-
• 13:45 Extending Visualization to Find Hard-to-reach Bugs
• 14:30 Memory Controller Re-use with ActiveIP
• 15:30 Design Activation with ActiveDesign
• 16:45 Closing Remarks
• 17:00 -Conclusion of Day-

Seminar Day 1 - Thursday, November 6th, 2008:

• 9:15 -Continental Breakfast-
• 9:30 Welcome Remarks
• 9:50 Jasper's Formal Platform
• 10:15 Architectural Verification Using JasperGold (User's presentation)
• 10:00 -Break-
• 11:15 Replacing Simulation Tasks with Formal (User's presentation)
• 11:30 Leveraging Different Verification Methodologies for Overall Productivity
• 12:00 -Lunch-
• 13:00 Hunting for Dangerous X's (User's presentation)
• 13:30 X Validation with Jasper's Technology
• 14:00 Formal Verification Deployment (User's presentation)
• 14:45 -Break-
• 15:00 Formal Engines and Optimizations for Capacity
• 16:00 Efficient Uses of State-space Tunneling
• 16:30 Validation of a Post-silicon Bug Fix (User's presentation)
• 17:00 Post-silicon Debug
• 17:30 -Conclusion of Day-
• * Cocktail reception with hors d'oeuvres immediately following. *

Seminar Day 2 - Friday, November 7th, 2008:

• 9:15 -Continental Breakfast-
• 9:30 Technology Advances and Roadmap
• 10:30 Motivation for Design Reuse (User's presentation)
• 11:00 -Break-
• 11:15 ActiveIP/ActiveDesign Introduction
• 11:30 ActiveIP/ActiveDesign Technical Presentation/Demo
• 12:30 -Lunch-
• 13:15 Deployment System and Training Program
• 13:30 Formal Methods Applied to a PCI-Express Transmit Retry Buffer (User's presentation)
• 14:00 Using Formal for Protocol Compliance
• 14:30 Using JasperGold for Designer Sand-box Tests (User's presentation)
• 15:00 -Break-
• 15:15 Mastering Proof Accelerators
• 15:45 Doing Formal Verification Early in the Design Process (User's presentation)
• 16:15 Extending Visualization to Find Hard-to-reach Bugs
• 16:45 Closing Remarks
• 17:00 -Conclusion of Day-

Continental breakfast and a buffet lunch are included on all days.

Location:
Network Meeting Center
5201 Great America Parkway
Santa Clara, CA 95054
408-562-6111

To ensure your place at this event, please complete the following registration form: