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| Across the Great Divide… |
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| By Shaun Giebel and Norris Ip, Jasper Design Automation |
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Are design and verification teams doomed to be always at odds? Across a great divide, even when they are simply down the hall (which is often not the case)?
Unfortunately, it is a truism that designers tend not to like to do verification and then downstream, verification teams suffer from this. It's often very difficult for verification teams to get designers’ time, advice, and effort to help during verification and debug. The advent of far-flung global project teams simply exacerbates this phenomenon.
Engineering managers who are responsible for both design and verification, for the whole project, understand that it makes extreme economic sense to verify designs earlier in the design flow. If designers can be convinced via incentives, initiatives, and the right tools to do more verification work, earlier and better return on investment is possible. It occurs because design and verification teams are more productive.
- Formal verification early in the design cycle has been shown to increase productivity by 25-50%.
- It results in higher quality the first time out, reducing iterations between design and verification.
- This leads to a great time-to-market benefit.
So, the goal is to ameliorate the relationship between design and verification teams. How? It’s formal in the entire SoC flow….
Imagine…..
What if there was a formal technology-based solution that provided databases and an analysis system for block-level design reuse, to accelerate design development and leverage RTL legacy design as well as commercial IP?
Such a solution exists: ActiveDesign™ from Jasper Design Automation. This software and services accelerates design development and reuse for important internal design blocks, as well as commercial IP comprehension and deployment. |
Figure 1: Formal-based Solution for Design Productivity and IP Reuse
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Formal verification technology applied at the block development and reuse level can solve problems for:
- Companies who promote design re-use of internally developed IP
- SoC designers who use internal or commercial IP
- Commercial IP vendors who want to proliferate their IP while reducing support costs
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There are two basic use cases for design and IP leverage:
- Creating and evolving new RTL
- Exploring, evolving and consuming legacy and third-party IP
While creating RTL, there are a number of activities that are critically important for correct and robust RTL. The values include: |
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| Design Phase |
| Basic verification |
Enables first level of verification in the design
Provides a framework to write and validate assertions
Delivers improved RTL robustness |
| Behavioral indexing |
Benefits for legacy blocks and post-design |
Improved debug |
What-if analysis
Correlate functions and RTL
Find bugs that would be almost impossible to detect in simulation |
| Incremental RTL changes are easily checked for correctness |
Consistent RTL code evolution and modification |
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For RTL design, “Formal techniques are well suited for the RTL design process. Unlike procedural testbenches, assertions can be written and tested as the RTL is implemented. In addition, the design exploration capability of Jasper’s tools helps the designer create assertions and explore the basic functionality much earlier which results in increased quality in the design cycle,” stated Faisal Haque, Director of Engineering, Qualcomm.
In the second use case, the goal is rapidly exploring and consuming (deploying) existing legacy and third-party IP. The value is in: |
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| Exploring/Consuming IP Phase |
Targets efficient design reuse |
Accelerates knowledge transfer Breakthroughs in design comprehension |
| Executable specification analysis |
Quick implementation startup since key functionality is dynamically displayed |
Behavioral tracing |
Correlation of RTL and functionality of the code helps debug: manipulate scenarios and check against design intent |
| Automatic stimuli generation/exporting |
Accelerates validation phase and programming sequence generation and analysis |
Figure 3: Knowledge Transfer and Leverage Phase |
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Formal technology and methodology delivers more assurance, and formal often surpasses simulation. “Formal verification helps in the discovery of subtle RTL issues which are difficult or even impossible to detect in simulation. We strive to thoroughly verify critical logic in these complex designs to ensure discrepancies never have an impact on silicon, and Jasper helps us towards achieving that goal,” stated Paul Tobin, Director, Verification Center of Expertise at AMD.
Technologies Underlying a Formal-based Solution
Many technologies need to work together for a solid solution for design and re-use, primarily in the areas of visualization, behavioral indexing to create a database of behaviors, and the formal engines which fuel the solution. These are shown in the table below, for Jasper ActiveDesign. |
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Figure 4: Interactive Technologies Underlying Formal-based Solution
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Interactive technologies provide accelerated RTL development with legacy design and IP reuse.
Behavioral Indexing™ is a capability for iteratively extracting, indexing, and storing relevant design behaviors in a database. It creates an executable specification and promotes design understanding and leverage.
Visualize™ provides graphical and waveform views of functionality and dependencies, with shorter iteration cycles for exploration, understanding behaviors, and root cause analysis. Promotes accelerated RTL development and debug; leveraged legacy design and IP. |
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| These technologies work together to provide direct controllability of traces and enables rapid exploration of “what-if” scenarios. Waveforms can be automatically generated without a testbench and easily reconfigured to explore and document any design functionality. With Behavioral Indexing you can extract, index, and store data about the design behaviors. Active annotation in the trace window provides instant information about these behaviors, which significantly improves the communication of the design intent to other engineers and teams. The Visualize technology can be used to group behaviors together to investigate higher level functionalities, which can then be captured as a recipe in the database for future reference and used by other teams who are consuming the IP. Any recipe in the database can be modified to investigate other “what-if” scenarios by simply drag-and-dropping other behaviors into the recipe. This significantly increases knowledge transfer and design comprehension compared to conventional methods like static waveforms contained within a document. |
Figure 5: Visualize and Behavioral Indexing |
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Figure 6: QuietTrace |
QuietTrace™ results in reduced designer iterations and simplified debug, with fewer trace events, and isolates behaviors relevant to designer queries. On-demand temporal smoothing of selected traces and signals, as shown below:
Implication Analysis™ is enhanced incremental behavioral analysis, with evolutionary RTL comparison. It compares multiple RTL revisions with incremental indexing and highlights the effect of design changes with precise differences in behaviors.
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Even before a design change has been made, Implication Analysis can provide information about signals and behaviors that could potentially be impacted. Once an RTL change has been implemented there are numerous metrics to quickly see all aspects of the design that have been impacted. Information such as changes in coverage, trace lengths, and exercised behaviors all provide invaluable feed back to the designer. Implication Analysis can quickly tell you if the new changes in the RTL have broken any existing features, or even if you have increased the latency in the design. |
Figure 7: Implication Analysis |
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Interactive technologies provide accelerated RTL development and unsurpassed knowledge transfer of the design intent and functionality. ActiveDesign and the underlying technologies provide an excellent solution for RTL development, including early debug, incremental RTL changes for consistent code evolution, accelerated verification with reduced need for simulation, and design confidence.
Knowledge transfer of the design intent and functionality for consuming the IP (verification and reuse) is easier and more comprehensive, with benefits such as RTL exploration and what-if analysis, accelerated verification of modifications, reduced need for simulation, and automatic, documented design confidence in an executable database. |
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Applications Survey
A recent survey of over 50 engineers and engineering managers showed that formal technology was deemed very important for the following three applications, among others:
- RTL Block Verification
- RTL Development
- Design and IP Leverage
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The data on the relative importance for these applications, and their sub- applications, based on the survey, is graphed below: |
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Figure 8: Survey of Applications and Adoption
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ActiveDesign employs numerous technologies to solve the most important design and verification challenges and can provide a tremendous ROI value in all stages of the SoC design cycle and can be applied months before any simulation testbenches are available. Formal verification solutions from Jasper Design can be used to evaluate and capture design trade offs including verifying architectural decisions even before any RTL is written. Capturing the design intent in an executable database to transfer across all teams will significantly reduce design and verification iterations. |
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In brief, formal technology can minimize the cost of communication between design and verification teams (and all IP consumers), thereby increasing the quality and time-to-market.
Summary |
Formal verification can indeed solve the lacuna between design engineers and verification teams. Jasper Design Automation’s ActiveDesign delivers an analysis system and databases for design development and reuse which unifies the teams, even for geographically remote teams. Powered by Behavioral Indexing, Implication Analysis, and Visualize technologies, Jasper formal solutions can accelerate design and IP creation and leverage.
As John Goodenough, Director of Design Technology at ARM has commented: “ARM is applying Jasper technology to the design and verification of increasingly sophisticated IP, with a view to increased assurance levels, reduced verification effort, and lower risk and support costs.”
Jasper offers a portfolio of solutions spanning both JasperGold and ActiveDesign. All apply formal technology to leverage and accelerate your design success. Customers rely on Jasper to solve their most critical project challenges and have increased productivity, shorter schedules, and mitigated risk. For ActiveDesign, this means lower development and reuse costs by enabling design efficiency and IP leverage, exploring, designing, developing, verifying, and re-targeting the block for leverage in multiple new environments. Formal verification unleashed for targeted ROI. |
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| Additional Resources: |
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Shaun Giebel, field applications engineer at Jasper Design Automation, received a BS in electronics engineering technology from DeVry Institute of Technology, Calgary, and an MS in electrical engineering from Villanova University.
Norris Ip, director of engineering at Jasper Design Automation, received a PhD in computer science from Stanford Univ., Calif., and a Masters / Bachelors in computer science from the University of Oxford, United Kingdom. |
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