Jasper and its Japanese distributor, CyberTec, conducted a survey at EDSF 2010 of more than 120 Japanese engineers and engineering managers from leading semiconductor suppliers, about the applications of formal verification and where it has the most business impact for targeted ROI across the SoC development cycle.  The survey results indicated that RTL block verification; RTL development; design and IP leverage; protocol certification, and low-power design verification are the top five most important applications, closely followed by silicon debug, chip integration, and architectural analysis early in the design cycle.

The following chart illustrates where formal verification delivers the greatest ROI for these companies: