| Technical
Papers |
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| Ensuring Correctness Where It Matters
Most |
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| Formal functional
verification has matured to the point where it is
far easier for users to adopt than ever before.
Yet, despite the advances, many users have not seen
the promised gains in productivity from formal.
The most common reason for this is the unstructured
way formal has been traditionally applied in the
verification environment. In this paper, we outline
a simple methodology for effectively planning a
production verification flow that easily integrates
formal verification into an existing simulation
environment. We also show how to effectively deploy
a tiered application of formal verification within
a project based upon end user skill set and comfort
level with the technology. The end result is a production-proven
verification flow that effectively integrates both
formal and simulation, and provides a predictable
verification schedule with measurable improvements
in design quality. |
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| Where Should I Use Formal
Functional Verification? |
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| With innovations in
formal technologies and methodology, the benefits
of formal functional verification apply in many
more areas. Although a generic awareness of where
formal functional verification applies is useful,
understanding the “what” and the “why”
leads to greater success. Clearly, if we understand
the characteristics of areas with high formal applicability,
we can identify not only which blocks are good candidates,
but also what portions or functionalities of the
blocks will give the greatest return on the time
and effort invested. In recent years, we have come
to realize that although we can apply formal to
entire blocks, it can be more valuable to apply
formal partially within blocks by choosing the functions
that have the highest return. This paper will aid
the reader in understanding where, why and how to
apply formal for the highest return. |
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| ABV: The On-ramp to Formal Verification |
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| Formal Assertion
Based Verification (ABV) has helped spread the use
of formal verification in the design community.
Reusing assertions already put in place to aid simulation
provides greater bug detection with only a slight
increase in effort.Formal verification has the additional
benefit of running earlier in the design process
than simulation. This paper introduces Formal ABV
using JasperGold® Verification System from Jasper
Design Automation. The easy use model, powerful
debugging capabilities, and scalable verification
capabilities combine to make this an excellent overall
solution for any organization considering using
formal verification as part of a production verification
flow. |
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| Easy Structured Verification Planning
Using GamePlan™ Verification Planner |
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| Today’s integrated
circuit verification has many pitfalls. One of the
most significant, and yet avoidable, is the lack
of a solid verification plan at the beginning of
the process. Effective verification planning adds
predictability into the verification flow by specifying
exactly what needs to be tested. Planning also provides
the necessary structure to identify key areas where
complementary verification technologies, such as
simulation and formal verification, can each be
applied effectively. In this paper, a methodology
of easy, structured verification planning is introduced
using GamePlan™ Verification Planner - a freely
available tool from Jasper Design Automation. By
providing structure early in the verification process,
verification teams can easily implement solid plans
to guide their work, seamlessly integrate formal
verification and simulation together, and provide
solid measurements of verification progress throughout
the development cycle. |
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| >> Please
click here to request any of the White Papers above. |
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