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Jasper ActiveDesign EDN Innovation Award Finalist
Active Design with Behavioral Indexing™ has been named a finalist for the 20th Annual EDN Innovation Awards. ActiveDesign is one of five EDA tools competing for the prestigious award in the front-end analysis and synthesis category. More... |
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Japanese Design and Verification Teams Report High ROI with Jasper
Jasper and its Japanese distributor, CyberTec, conducted a survey at EDSF 2010 of more than 120 Japanese engineers and engineering managers from leading semiconductor suppliers, about the applications of formal verification and where it has the most business impact for targeted ROI across the SoC development cycle. More...
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Panelists Look at IP Quality Versus Design Productivity
A fundamental problem in the industry is to analyze and implement the tradeoffs between improving IP quality and losing design productivity. During a recent panel discussion at the IP-ESC 2009 Conference in Grenoble, France, IP buyers and sellers confronted experiences and issues. More...
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IP-företagen har mognat (Swedish)
Det mesta verkar vara löst för den som vill konstruera med färdiga IP-block. Framför allt fungerar verifieringen tämligen smärtfritt. Men energistyrningen blir allt mera komplicerad.
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IP/ESC'09: dall'IP ai sistemi embedded (Italian)
Dai blocchi IP ai SoC ai sistemi embedded: la 18° edizione IP/ESC'09 tenutasi a Grenoble nel mese di dicembre ha offerto agli oltre 500 intervenuti un significativo spaccato dell'evoluzione e delle problematiche legate al mondo sempre più complesso della progettazione elettronica. More...
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Using Formal Verification for SoC Integration
SoC Integration poses verification challenges that have steadily become more complex, as designs continue to grow. Today's SoCs combine large IP blocks, high-speed IOs, complex low-power implementations, and custom debug and test logic.
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Newest Jasper Formal Technology
This JasperGold/JasperCore release delivers unprecedented deep proofs and bug-hunting, while adding value across the entire spectrum of formal verification design applications, from architectural and RTL verification to post-silicon debug.
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May You Live in Interesting Times
These indeed are interesting times for our industry. We live in a connected world with a new generation of users who demand more and more functionality in smaller and smaller packages. They take high performance and low power for granted, and the semiconductor design ecosystem continues to do amazing work to turn those expectations into reality.
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Nikkei Tech-on! (Japan)
米Jasper Design Automation, Inc.は，2010年1月28日と29日にパシフィコ横浜で開催のEDS Fair 2010で，同社のフォーマル検証ツール「JasperGold/JasperCore」の最新版をリリースすると発表し…
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Formal is More Than Just Alive and Well. It is Thriving!
Olivier Coudert started it with his blog entry a while back. In it he had this to say "Looking at the DAC submissions this year though, I am puzzled by the overwhelming number of papers focused on increasing simulation speed and coverage, as opposed to the handful of papers discussing formal techniques. And this year is not different from last year. And the year before last. Does that mean there is a lack of innovation in formal verification core techniques?"
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EASii IC Working With Jasper To Promote Formal Innovations In Europe
Jasper Design Automation announced it is working with France's EASii IC, a well-known European electronic-design consulting company, to accelerate the adoption of formal verification methods and increase understanding of how they apply across the entire spectrum of chip design, from architecture to signoff, with its customers.
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Just for Fun!
A "must see" video that tells it like it is, in the wacky world of high-tech sales.
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Just for Fun!
How Engineers and Managers Communicate: A Video Parody.
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DAC 2010
June 13-18
Anaheim Convention Center, California, USA |
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To meet with the design and verification deployment experts at Jasper at any of the above conferences,
please send email to info@jasper-da.com or call 1.650.966.0266.
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www.jasper-da.com
Jasper Design Automation, 100 View Street,
Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840 |
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