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 DAC 2010 is fast approaching!
Please visit Jasper, Booth 1337, to learn about the latest advances in formal verification technology.
Register now for informative product demos with Jasper experts, and discover how we deliver targeted ROI across the spectrum of applications for formal from architectural exploration to post-silicon debug.
Jasper is participating in numerous industry and technical programs: for complete details visit the
Jasper Events Page on our website. Highlights include:
DAC User Track Technical Sessions / Case Studies in Formal Verification
Industry Events
- DAC Colocated Event: Choosing Advanced Verification Methods: So Many Possibilities, So Little Time, Adam Morawiec, ECSI
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DAC Career Workshop: More Than Core Competence - What it Takes for Your Career to Survive, and Thrive! Sponsored by Women in Electronic Design (WWED),
Panelist Kathryn Kranen, Jasper President and CEO, Co-Chair Holly Stump, Jasper VP Marketing
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DAC Pavilion Panel: High-School Panel - Teens on Tech, Moderated by Kathryn Kranen, Jasper President and CEO
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Matt Hsu, Matthew A. Hsu Consulting
Matt Hsu discusses formal verification and how Jasper has helped in a wide variety of verification contracts with major electronics companies.
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Viewpoint: Maximizing the value of your IP
Some amazing statistics: Third-party semiconductor IP is now a $1 billion per year business, with thousands of suppliers. One-third of all logic in a design is now reused legacy IP, and that figure will grow to 50 percent by 2015. |
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Formal Verification for Challenging Low-Power Designs
Low-power designs have become ubiquitous in today’s world. Designers of consumer and mobile products create aggressive low-power designs to compete on extended battery life. Tethered device designers (e.g., servers and routers) want to reduce cost of ownership. |
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Formal Analysis: A Valuable Tool for Post-Silicon Debug
The verification of today’s bleeding-edge chips requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug.
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EDA technologies to watch out for at DAC 2010
It may occasionally feel that innovation in the EDA industry has flat-lined along with the revenue. But using our definition of innovation, it hasn’t. EDA technology’s objective must surely be to increase its users’ effectiveness and efficiency - and continuous improvement is generally the way to get there. |
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The Holy Grail of Unified Coverage: What’s the Reality?
Verification engineers and their managers are intrigued by the idea of a unified coverage standard that can combine data from heterogeneous sources (different verification methods, tools from different vendors, etc.) not only into a single database, but into a single integrated coverage measurement and metrics system. This is a wonderful dream that is best approached step-wise.
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OCP-IP Papers & Presentations
OCP and Verification of Configurable OCP Interfaces –
John Moondanos, Lawrence Loh, Holly Stump, Jasper Design Automation
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What is Formal Verification?
Functional verification is a critical element in the development of today’s complex digital designs. Hardware complexity growth continues to follow Moore’s Law, but verification complexity is even more challenging.
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Twitter of RTL Design – Welcome to Behavioral Indexing!
If you haven’t heard of Twitter you perhaps are living in an internet vacuum J On a positive note, the reach and impact of SNS (Social Networking Sites) into our internet life is hard to ignore – whether it is Twitter, Facebook, LinkedIn etc. To me, a successful SNS tries to capture “what is in going on in your mind right now”?
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Jasper’s Kathryn Kranen Re-Elected As EDAC Vice Chair
Jasper Design Automation, provider of advanced formal technology solutions, today announced its President and CEO, Kathryn Kranen, has been re-elected as Vice Chair of the Electronic Design Automation (EDA) Consortium. As a board member for the past six years she has been active in promoting the contributions of private EDA companies, as well as demonstrating the significant return on investment (ROI) EDA brings to the semiconductor industry.
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SAME Conference
October 6-7
Sophia Antipolis, France
"New Technologies in Formal Verification for Increased Design and Verification Productivity"
by Adam Morawiec and Norris Ip, Jasper Design Automation
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To meet with the design and verification deployment experts at Jasper at any of the above events,
please send email to info@jasper-da.com or call 1.650.966.0266. |
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www.jasper-da.com
Jasper Design Automation, 100 View Street,
Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840 |
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