Please visit Jasper at DAC 2009 in San Francisco, Booth #3767, for demos of exciting new capabilities in JasperGold and ActiveDesign formal verification solutions. Other Jasper DAC highlights include a Forum presentation with Raffaele Guarrasi from ST ... Rajeev Ranjan on the Verification Debug panel ... Kathryn Kranen moderating a DAC Pavilion panel ... Holly Stump on the Women in Technical Careers panel ... and more! Contact us to set a meeting: info@jasper-da.com or 1-650-966-0266.
 
ARM
  ARM Selects Jasper for Formal Verification of IP
ARM chooses Jasper, a leader in formal technology, to reduce verification costs, increase quality and design enablement. John Goodenough, ARM Director of Design Technology, commented, ARM is applying Jasper technology to the design and verification of increasingly sophisticated IP, with a view to increased assurance levels, reduced verification effort, and lower risk and support costs. More...

AMD
  Jasper, AMD Ink Long-Term Formal Verification Deal
Jasper Design Automation today announced it has signed a long-term agreement with AMD (NYSE: AMD) to place JasperGold formal verification technology in AMD design centers worldwide.
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Jasper on John Cooley's DeepChip
Questions and answers about Jasper technology and business on John Cooley's Deepchip.
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  Jasper Announces University Program
Jasper Design Automation, provider of advanced formal technology solutions, today announced the Jasper University Program, advancing the use and understanding of formal techniques in select universities worldwide.
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  IC Journal on ActiveDesign "But What Does It Mean?"
We’ve all been there before. We get handed a design that someone else did, most likely someone that’s no longer around, no longer accessible. Into our laps it falls, warts and all. Only, it’s hard to tell which behaviors in the design are warts and which are wants. More...

  Mixing Formal and Dynamic Verification, Part 1
Over the last few years, there has been a noticeable uptick in the use of formal verification to augment dynamic verification. Given that both techniques leverage assertions, one would assume that there would be a great deal of collaboration between dynamic testbenches and formal property checking, the user teams and the tools. More...

 

JasperGold Adds Proof Accelerators For Fast, Thorough Verification
Jasper Design Automation, provider of advanced formal technology solutions, today announced the addition of three new Proof Accelerators to its JasperGold® Verification System. Proof Accelerators increase the power, the capacity and the performance of formal verification by significantly reducing the state-space of a design through optimized modeling of common design functions. More...


 

Jasper Patent Speeds Debug During Verification
Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded U.S. Patent No. 7,506,288 for "interactive analysis and debugging of a circuit design during functional verification of the circuit design." More...


 

Jasper Extends Formal Verification Technology Lead With Four New Patents in Portfolio
Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded four new U.S. patents. The recent patents further advance the company’s formal technology, according to Jasper CTO Rajeev Ranjan. More...

 
 
  Richard Goering Interviews Kathryn Kranen
Learn about Jasper applications and targeted ROI.
Watch video...

  Demonstrating Targeted ROI
Chip designers worldwide have told Jasper that they’re looking for something fundamentally different to help them with their technical and business problems. We’ve coined the term "Targeted ROI" to describe the process.
More...

 

New Flash Overviews:
Jasper Design Automation
JasperGold Solutions
ActiveDesign Solutions


 

Kathryn Kranen: Celebrating Natural Selection in EDA
Jasper just received an additional $7 million in VC funding, announced February 18th, so it’s not surprising that Kranen’s enthusiasm for the industry continues unabated. She says EDA is neither dead nor dying – with a caveat. Per Kranen, a process of natural selection is playing itself out in the industry. More...


 

EDN Guest blog: Kathryn Kranen
Since Jasper raised its D-round of venture financing during Q4 of 2008, many people have asked me what it takes to close a round in today’s tough economic climate. Of course, the answer depends greatly upon your company’s stage of development, and ultimately, the market opportunity for your products. More...


  Jasper: OCP-IP DATE Presentation
OCP and Verification of Configurable OCP Interfaces
by Øystein Kolsrud, Holly Stump

  Video Interview: CTO Rajeev Ranjan, DesignCon 2009
This video encompasses industry executive Rajeev Ranjan's professional views and opinions captured on the Road to DesignCon 2009.
Watch video...
 
 
  DV Club
"Is it Time to Declare a Verification War?"
6/1/09
Boston - Westford Regency Westford, MA

  21st International Conference on Computer Aided Verification - CAV 2009
6/26/09 - 7/2/09
World Trade Center Grenoble, Grenoble, France

Jasper sponsors CAV

 

12th International Conference on Theory and Applications of Satisfiability Testing
6/30/09 - 7/3/09

Swansea, Wales, UK

Contact Ziyad Hanna, Program Committee


  Design Automation Conference (DAC)
July 27 - 30 2009
Moscone Center, San Francisco, CA

Come see Jasper DAC demos of JasperGold and ActiveDesign:
Booth #3767, contact Peggy Gallar to set a meeting at info@jasper-da.com or call 1-650-966-0266

- Jasper Exhibitors Forum: Presentation with Raffaele Guarrasi from ST
- Verification Debug panel: Rajeev Ranjan
- Kathryn Kranen is moderating a DAC Pavilion panel
- Holly Stump is on the Women in Technical Careers panel
 
To meet with the design and verification deployment experts at Jasper at any of the above conferences,
please send email to info@jasper-da.com or call 1.650.966.0266.

 
www.jasper-da.com
Jasper Design Automation, 100 View Street, Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840

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