Jasper User Group
Enthusiasm For Formal Reigned At Jasper User Group Meeting 2009: The sixth annual Jasper Users Group meeting, November 2-3, was a tremendous success, marked by both the quality and quantity of user presentations: up 50% from last year! User and Jasper exec presentations highlighted all eight applications in the “Spectrum of Applications” for formal. Designs described by the presenters included very high-end communications and processing chips - true state-of-the-art designs from the leaders in their field.

  Applying Formal Methods to a PCI-Express Transmit Retry Buffer
Sun designers and architects now view formal as a tool to understand and expose specification holes and errors. Exploring corner case scenarios early leads to cleaner, more robust implementations. And formal verification can help promote design leverage and reuse. More...

 

Survey of Chip Designers on the Value of Formal Verification Across the Spectrum of Applications
Over 50 engineers and engineering managers were surveyed at DAC 2009 by Jasper Design Automation as part of a market research and analysis program examining how designers use formal verification across the design cycle.
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  Formal Methodology Validates Cache-Coherence Protocol
Why wait until RTL is available to root the bugs out of a complex system design? Formal verification methods can be leveraged at the architectural level.
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  IEEE International High Level Design Validation and Test
Conference paper:
"A Symbolic Execution Framework for Algorithm-Level Modelling" by Ziyad Hanna and Tom Melham

 

Imagining New IP Architectures: Formal Verification Conquers the Void
ARM Techcon paper by Sebastian Skalberg
Download Paper


 

Jasper Product Demos
- JasperGold Full Video Demo
- ActiveDesign Full Video Demo


 

Across the Great Divide
Are design and verification teams doomed to be always at odds? Across a great divide, even when they are simply down the hall (which is often not the case)?
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Survey has designers assign ROI to verification chores
Jasper Design Automation surveyed over 50 engineers and engineering managers at DAC 2009 as part of a market research and analysis program examining how designers use formal verification across the design cycle.
More...

 
 
  Lawrence Loh Promoted to Vice President of Worldwide Applications Engineering at Jasper Design Automation
Jasper Design Automation, provider of advanced formal technology solutions, today announced that Lawrence Loh has been promoted to Vice President of Worldwide Applications Engineering. In his new role, Loh will continue and expand his responsibility for the company’s applications engineering and methodology development, reporting directly to Jasper President and CEO, Kathryn Kranen. More...

  Top 10 women in microelectronics
There is no better time than a global economic recession to examine the keys to successful corporate governance, and EE Times is honored that the ten selected women called a brief halt to their frantic business schedules to share in their diverse experiences. More...

  Jasper Design Automation and Chalmers University of Technology Receive Prestigious Swedish Research Council Grant For Joint, High-Level Verification Research Project
Longtime collaborators Jasper Design Automation and Chalmers University of Technology (Göteborg, Sweden) have begun a joint research project to study formal verification of high-level circuit models, partially funded by a prestigious grant from the Swedish Research Council (Vetenskapsrådet), which awards grants to stimulate knowledge transfer between academia and industry. More...

  Jasper Names HASS Technology Distributor for China
Jasper Design Automation, provider of advanced formal technology solutions, has named HASS Technology as its distributor in China and Taiwan. More...

  Teens and Tech: What’s Hot and What’s Not!
Certain things will come as no surprise to anyone who is a parent; all said they are online pretty much the entire day. What might be less known is what they are doing there. More...

  It's the Customers
Jack Horgan interviews Kathryn Kranen, President and CEO of Jasper Design Automation.
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  EDACafe Interviews Kathryn Kranen at DAC 2009
Learn about Jasper applications and targeted ROI.
Watch video...
 
 
  DAC 2010
June 13-18
Anaheim Convention Center, California, USA

DAC is very enthusiastic about User Track submissions! Jasper encourages all users to consider submitting a presentation for DAC 2010 in Anaheim, CA. More information on submissions is available here. Please contact
Holly Stump, Jasper VP Marketing, to mobilize any support needed from Jasper.

  EDSFair 2010
January 28-29
Kanagawa, Japan

EDSFair is a large-scale tradeshow sponsored by JEITA that showcases the latest IC design tools, methodologies, manufacturing solutions, design services, and many other technologies that affect today's electronic circuits and systems. Jasper and Cybertec will demonstrate the latest formal verification technology and applications, with Targeted ROI.

 

IP'09 Conference
December 1-3

Grenoble, France

Kathryn Kranen will speak on 2 panels, and deliver an invited paper.
IP Reuse vs. IP Leverage: What's the difference, and what are the issues?
Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?

Invited Talk: High Level Modeling and Verification for IP-Based Systems


  Formal Methods in Computer Aided Design / FMCAD 2009
November 15-18
Austin, Texas, USA

Panel: "What will be the next breakthrough solutions in formal?"
 
To meet with the design and verification deployment experts at Jasper at any of the above conferences,
please send email to info@jasper-da.com or call 1.650.966.0266.

 
http://www.jasper-da.com/
Jasper Design Automation, 100 View Street, Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840

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