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Design Automation
Conference (DAC)
Anaheim Convention Center, Anaheim, CA, 6/9/08 -
6/13/08
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Jasper
Design Automation, the leader in successful deployment
of production proven formal verification solutions,
will demonstrate its Formal Verification Unleashed™
- an advanced verification methodology supported
by best-in-class formal verification solutions,
to exhaustively verify complex designs at any
stage in the design flow, from architecture-level
to first silicon. Learn how industry-leading companies
worldwide have applied high-capacity, high-performance
formal verification solutions from Jasper Design
Automation to successfully prove protocols and
executable specs, to design, explore and debug
RTL, to ensure correctness of block-level functionality
and to conduct fast and exhaustive post-silicon
debug.…More..
- Kathryn Kranen, CEO of
Jasper Design Automation, will speak at the
ACM Turing Award plenary session on Monday,
June 9, 2-4 pm.
- Jasper Design Automation's
Kathryn Kranen Moderates DAC Pavilion Panel
on Today's Consumer at the 45th Annual Design
Automation Conference
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Ziyad Hanna will chair the Formal Verification
Technology session at DAC. This session presents
four papers that advance the state-of-the-art
in formal verification technology, making
formal verification tools more efficient and
usable. Speakers include: In-Ho Moon, Synopsys,
Inc., Malay Ganai, NEC Labs America, Yan Chen,
Portland State Univ., and Paul T. Darga, Univ.
of Michigan.
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International
Conference in Computer Aided Verification
(CAV)
Princeton,
NJ, 7/7/08 - 7/14/08 |
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Haifa
Verification Conference
10/27/08 - 10/30/8 |
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Formal
Methods in Computer Aided Design (FMCAD) 2008
Portland, OR
11/17/08 - 11/20/08
...More
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Jasper
Design Automation Targets Next Generation System-On-Chip
Design With Growing Portfolio Of Innovative Formal
Technology Patents
Jasper Invests Heavily
In Advancement of Formal Technology; U.S. Patent
And Trademark Office Grants Seven Patents |
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Jasper
Design Automation Unveils Its Production Proven
Proof Accelerators For Rapid and Exhaustive Verification
of Intractable Datapath Designs
Delivering Orders of
Magnitude Greater Coverage than Simulation alone,
JasperGold® Verification System Modeling Extensions
Reduce Complexity, Improve Performance and Dramatically
Increase Formal Capacity |
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Using
formal verification for post-silicon debug
The burden that system-on-chip
(SoC) design complexity places on logic designers
and verification engineers is well-documented. But
what about the silicon bring-up team? What happens
when a critical bug slips through to silicon? Further
costly design re-spins must be avoided, so it is
absolutely essential to thoroughly debug the silicon
as quickly as possible. But that’s very difficult
because of the limited visibility into silicon.
...More
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Verifying
Configurable Verification Interfaces Using OCP
The Open Core Protocol
(OCP) is a synchronous socket interface specification
that is widely used in the semiconductor industry
today for System-on-Chip (SoC) designs. The flexible
nature of the implementation makes it widely applicable
to many different hardware applications that require
a simple, robust data transfer protocol...More
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Formal
Verification Takes To "Sandbox"
The latest release
of Jasper Design Automation's JasperGold formal
verification suite includes the InFormal Design
Analyst, a tool aimed at designer "sandbox"
verification without need for development of properties
or a testbench for simulation. JasperGold v4.3 also
sports performance gains as well as advances in
property modeling and ease of use...More
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Verification
with Jasper's Product Family
Jasper formal verification
technology delivers compelling benefits throughout
the entire SoC design flow, from RTL debug through
verification and regression test to post-silicon
debug. JasperGold Verification System provides rapid
bug detection and debug as well as end-to-end full
proofs of expected design behavior. It is the only
production-proven formal verification solution that
enables seamless scalability from formal assertion-based
verification (ABV) to exhaustive end-to-end proofs
of microarchitecture-level properties. Its powerful
analysis capabilities and ease of use make it ideal
for early-stage bug hunting as well as ensuring
the highest confidence possible in your design functionality
via end-to-end full proof. ...More
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Early
RTL Verification with JasperGold
Formal verification
with JasperGold® Verification System is a powerful
tool for RTL designers as well as for verification
engineers. JasperGold System allows RTL designers
to verify early, when it counts, and to explore
the behavior of internal and commercial IP blocks
they are incorporating. Finding a bug early in initial
RTL design instead of later in the verification
stage can shave significant time off the overall
project schedule. Not only is the repair cost less
than later in the flow, but there are no futher
design dependencies added on top of the bug to complicate
the fix. Formal verification is possible at the
earliest stages of the design flow because it does
not depend upon costly testbench development to
run. Formal verification has the most exhaustive
coverage of any verification method, making it ideal
for early bug detection and removal. JasperGold
formal verification has numerous features to make
formal easy for RTL designers who don't have time
to learn complicated tools or languages. This enables
powerful formal technology to be applied by designers
early in the verification flow for maximum benefit....More
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Post
Silicon Debug with JasperGold
Debugging silicon is
a challenging task, one that creates urgency and
stress within the SoC bring-up team. Production
and time to market pressures demand fast turn-around
time for this difficult problem. Formal methods
are unique among EDA tools in tackling post-silicon
bugs. JasperGold® Verification System formal
verification platform tackles the problem due to
its ability to resolve verification ambiguity for
significant blocks with high level requirements.
Since these complex properties are exactly the type
used in post-silicon debug, JasperGold formal verification
is unique in its ability to handle the associated
capacity issues of silicon debug applications...More
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Jasper
Design Automation Adds Tom Melham And Moshe
Vardi To Its Technical Advisory Board
Verification
Industry Visionaries Contribute To Jasper's
Formal Technology Development ...More
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EDA
Consortium Elects Officers and Board Members
SAN JOSE, California,
April 2, 2008 - The Electronic Design Automation
(EDA) Consortium announced today that it has
elected a nine-member Board of Directors and
officers to serve the organization through
spring 2010 Walden Rhines, chairman and CEO
of Mentor Graphics Corporation, was elected
chairman by the new board. Aart de Geus, chairman
and CEO of Synopsys and Kathryn Kranen, president
and CEO of Jasper Design Automation, were
elected vice-chairmen....More |
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www.jasper-da.com
Jasper Design Automation, 100 View Street,
Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840 |
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