 |
|
 |
|
|
|
| |
|
|
| |
Jasper Design Automation Raises $7 Million in Series D Funding
Jasper Design Automation, leading EDA provider of design, verification, and reuse solutions leveraging formal technologies, today announced it has raised $7 million in Series D financing. The investment round was led by new investor, ZenShin Capital of Menlo Park. |
|
|
| |
Jasper is EDN Innovation Finalist!
Jasper Design Automation, provider of advanced formal technology solutions, today announced that its flagship product, JasperGold® Verification System, has been selected from among hundreds of nominations as a finalist for this year’s EDN Innovation Awards under the category of 'EDA: Design Analysis.'
|
|
|
|
|
|
|
|
|
| |
To subdue the enemy without fighting is the supreme excellence
"I am excited today to be able to talk about a new product that I had to keep quiet about for some time. First of all some disclosure. I am on the Technical Advisory Board of Jasper Design Automation and it was associated with that role that I first learned about some developments that they were working on." |
|
|
| |
Formal technology fuels 'behavior-based' RTL analysis
The burden that system-on-chip (SoC) design complexity places on logic designers and verification engineers is well-documented. But what about the silicon bring-up team? What happens when a critical bug slips through to silicon? |
|
|
|
|
| |
"Is it Time to Declare a Verification War?"
It is often said that verification is an art, but that has led us to statistics that show that success rates for chips are low. Perhaps it is time to think of it as war. In the words on Sun Tzu “If you know the enemy and know yourself, your victory will not stand in doubt”.
|
|
|
| |
Formal verification enables safe X handling
The use of unknown values (X states) can provide significant benefits in RTL verification, and can allow better logic optimization for synthesis. But uncontrolled or unexpected X propagation in simulation can also mask bugs, potentially leading to failures in silicon. |
|
|
|
| |
|
|
|
|
|
| |
| |
| |
DV Club
Dave & Busters, Milpitas, CA
March 19 2009
Brian Bailey addresses "Is it Time to Declare a Verification War?"
|
|
| |
 |
Design Automation Conference (DAC)
Moscone Center, San Francisco, CA
July 27 - 30 2009
Visit Jasper Design at booth #3767
Email: info@jasper-da.com, or call +1.650.966.0200 |
|
| |
|
To meet with the design and verification deployment experts at Jasper at any of the above conferences,
please send email to info@jasper-da.com or call 1.650.966.0266.
|
|
|
| |
 |
www.jasper-da.com
Jasper Design Automation, 100 View Street,
Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840 |
|
|
This message was sent by Jasper Design Automation,
Inc. Click
here if you prefer not to receive future
e-mail from Jasper Design Automation, Inc.
|
|
|
|
|
|
