Formal Technology Newsletter
Q4 2012

In The News

Jasper Releases Two Property Synthesis Apps Targeted at Early RTL Qualification and Coverage-Driven RTL Verification
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Jasper CEO Talks EDA Success – EE Times
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Innovation is Alive and Well in EDA – EDA Digest
By Kathryn Kranen
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Jasper Design's Kranen Talks Biz Models, Global Investment – EE Times
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Formal Methods for Power-Aware Verification - EE Times
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Formal Analysis for Security Data Paths - SemiWiki
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Jasper User Group Meeting

Jasper’s annual user meeting was held on November 12 & 13 and gathered designers, verification engineers and engineering managers from around the world to share the latest verification best practices. This year's conference included special presentations from AMD, ARM, Broadcom, Intel, Qlogic, ST Microelectonics, and many more. Topics included:

- Formal Verification at Intel – Past, Present, and Future
- Simplifying Subsystem Verification
- Deadlock Verification
- CPU Subsystem Verification
- Pre-verified Verification Components Enhancing System-level UVM Framework
- Design Approach to Verification
- Formal Verification at ARM – Heading for Mainstream
- Mitigating Coherency Related Risks
- Coverage Closure
- Security Verification
- Proofkit on Memory Control Block
- Formal Verification of Low Power Clocks and Resets
- Reverse Connectivity Flow

Jasper customers can view these presentations on our Formal Expert support site at: (log in required).

Video Tips

Jasper customers can now view tips on how to use Jasper's solutions more effectively at (log in required).

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