JASPER DESIGN AUTOMATION ACQUIRES SAFELOGIC CORPORATION

Merger to Accelerate Proliferation of Formal Verification


Mountain View, Calif. - January 12, 2005 - Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced that it has acquired Safelogic, the technology leader in Property Specification Language (PSL) based formal verification. The terms of the transaction were not disclosed. The acquisition brings together technology leaders in complementary areas within the formal verification market, creating a combined company with the EDA industry's strongest solution for verification and debugging of block-level designs using assertions and high-level requirements. The merged company has one of the formal industry's strongest engineering teams, with development sites in Mountain View, Calif., Berkeley, Calif., and Göteborg, Sweden.

"By combining Safelogic's automatic, push-button, high performance solution for assertion-based verification with Jasper's solution for high-capacity high-level verification and debugging, we will accelerate proliferation of our products by increasing ease-of-adoption for new customers," said Kathryn Kranen, president and CEO of Jasper. "The merged solution will give designers and verification engineers the ability to quickly and easily prove their assertions, as well as to reach full proof of high-level requirements on full blocks using Jasper's unique design tunneling technology. Safelogic's advanced implementation of PSL verification, together with Jasper's fast static debugging capability, gives design teams a powerful new way to deliver provably correct designs with a shorter, predictably finite verification schedule."

"Jasper and Safelogic are a perfect match for maximizing technology offerings and market opportunities," said Pär-Jörgen Pärson, chairman of Safelogic. "Jasper has focused on high-level interactive proof of block-level requirements, while Safelogic has focused on developing world-class proof engines for fast verification of PSL assertions with minimal user interaction. Jasper is strong in North America and Japan, while Safelogic is strong in Europe. The combined company can field the fastest, broadest formal verification solution across all geographies."

Advanced, complementary formal engines
Safelogic brings to Jasper one of the world's fastest formal proof engines. When integrated with Jasper's unique Precognitive engine, which automatically determines which parts of a design are relevant for a particular proof, this solution will give users the highest performing formal proof solution.

World's best assertion language support
Safelogic has long been involved in the development effort for the Property Specification Language, and has developed the market's most advanced implementation of PSL formal verification.

"Safelogic is widely recognized as having made a major contribution to the development of the PSL standard, particularly as it relates to formal proof," said Harry Foster, chairman of the IEEE-1850 PSL Committee and chief methodologist at Jasper Design Automation. "In contrast to the many rudimentary and incomplete implementations out there, Safelogic has the most comprehensive support of PSL in the formal industry. This, combined with Jasper's support of Verilog-based requirements and commitment to SystemVerilog Assertions, puts the combined company at the forefront of assertion language support."

Structure of the Transaction
The merged company will continue to operate under the Jasper Design Automation brand and will be based in Mountain View, CA. Pär-Jörgen Pärson has joined the Jasper board of directors, and Jonas Risberg, a Safelogic board member, will participate on Jasper's board as a board observer. All Safelogic employees became employees of Jasper Design Automation in December 2004, when the transaction closed.

About Safelogic
Founded in 1999, Safelogic is an EDA software company developing ground-breaking tools for improved formal verification of system-on-chip (SoC), application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) designs. For more information, please visit www.safelogic.se.

About Jasper Design Automation
Founded in 1999, Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company headquartered in Mountain View, California. Delivering breakthrough verification completeness, productivity and predictability, the JasperGold® Verification System solution formally verifies that complex design blocks meet their high level requirements, as defined by their specifications, without any testbench development. JasperGold Verification System automatically isolates bugs with a fast, unique debugging capability, trimming crucial months off the verification schedule. For further details on how to improve design quality, verification productivity, predictability and verification reuse, visit http://www.jasper-da.com.

#                      #                      #

Jasper Design Automation, the Jasper Design Automation logo, Tempus Quest, JasperGold Verification System and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

--
Editorial Contact:
Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153
francine@thinkbold.com