JASPER DESIGN AUTOMATION FORMS FORMAL VERIFICATION TECHNICAL ADVISORY BOARD

Design Verification Visionaries to Provide Research Insights and Experience to Jasper Management


Mountain View, Calif. - January 12, 2005 - Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced that it has formed a Technical Advisory Board (TAB) made up of world-renowned visionaries from the academic world in the field of formal verification. The TAB's purpose will be to advise Jasper's management team on academic research trends in formal verification, provide guidance on Jasper's technical product development, and to educate students on the commercial trends in formal verification. The initial members of the TAB include Alan Hu, associate head of the Department of Computer Science at the University of British Columbia; Sharad Malik, professor in the Department of Electrical Engineering, Princeton University; Satoshi Goto, professor at the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan; and Claudionor Coelho, associate professor at the Federal University of Minas Gerais, Belo Horizonte, Brazil.

"The charter members of our technical advisory board are all highly distinguished professors at top universities and greatly accomplished in industry as well as formal technology research," said Vigyan Singhal, founder and chief technical officer at Jasper. "We are honored that they have agreed to serve on the TAB, and are looking forward to working with them to chart the future of commercial formal technology. This is especially exciting in light of our merger with Safelogic, which brings together two of the most advanced formal technologies available today."

"Jasper has invented a breakthrough approach to formal functional verification that allows users to solve problems that were previously intractable," said Sharad Malik, who was previously on the technical advisory board for Verplex Systems. "In joining as a charter member of Jasper's TAB, I am excited to be a part of this innovative team that's delivering on the long-standing promise of formal verification - a reliable, scalable, exhaustive verification method for the masses."

Biography of Alan Hu
Dr. Alan J. Hu received his B.S. degree (with honors and academic distinction) as well as his Ph.D. from Stanford University, California.

Currently, he is Associate Professor and Associate Head of the Department of Computer Science at the University of British Columbia. For the past 15 years, his main research focus has been automated, practical techniques for formal verification. Prior to joining UBC, he was a Member of the Research Staff in the VLSI CAD division of Fujitsu Laboratories of America.

Dr. Hu won first place in the Westinghouse (now Intel) Science Talent Search in 1985, was a U.S. National Merit Scholar also in the same year, and was elected to Phi Beta Kappa in 1987. He has served on the program committee of most major CAD and formal verification conferences, and chaired or co-chaired CAV (1998), HLDVT (2003), and FMCAD (2004). He was a Technical Working Group Key Contributor on the 2001 International Technology Roadmap for Semiconductors.

Biography of Sharad Malik
Sharad Malik received his B. Tech. degree in Electrical Engineering from the Indian Institute of Technology, New Delhi, India, and his M.S. and Ph.D. degrees in Computer Science from the University of California, Berkeley.

Currently he is a Professor in the Department of Electrical Engineering at Princeton University. His research spans all aspects of Electronic Design Automation. His current focus areas are the synthesis and verification of digital systems and embedded computer systems. Dr. Malik has published numerous papers, book chapters and a book (Static Timing Analysis for Embedded Software) describing his research. His research in functional timing analysis and propositional satisfiability has been widely used in industrial electronic design automation tools.

He has received numerous awards, including Best Paper Awards at the International Conference on Computer Design, the Design Automation Conference (DAC), and the Design Automation and Test in Europe (DATE) Conference. He serves/has served on the program committees of DAC, ICCAD and ICCD and was the General Chair for DAC 2004. He is on the editorial boards of the Journal of VLSI Signal Processing, Design Automation for Embedded Systems and IEEE Design and Test. He is a fellow of the IEEE. He is currently serving as the Associate Director of the Gigascale Systems Research Center, a multi-university effort directed towards defining and developing system design methodology with a ten-year horizon.

Biography of Satoshi Goto
Satoshi Goto received his B.E. degree, M.E. degree and doctorate in Electronics and Communication Engineering from Waseda University.

After receiving his doctorate, he joined Central Research Laboratories of NEC where he worked for 31 consecutive years. He was General Manager of C&C Media Research Laboratories and Vice President in charge of computer, software and networking research. After leaving NEC in 2002, he became Chief Executive of Kitakyushu Foundation for the Advancement of Industry, Science and Technology. He became Professor at the Graduate School of Information, Production and Systems at Waseda University, Kitakyushu in April, 2003. He was also a Visiting Scholar at the University of California, Berkeley. In research, Dr. Goto worked on Computer Aided Design for VLSI, Artificial Intelligence approach to VLSI design and combinatorial optimization methods for large scale problems. He is the author or co-author of over 80 papers in VLSI design and Computer Aided Design.

He has served many conferences as an Executive committee member. Among those are the General Chair and Program Chair of ICCAD, General Chair of ASPDAC and committee member of DAC and ISCAS. He was a member of the Board of Director of the IEEE Circuits and Systems, the Institute of Electronics, Information and Communication Engineering and Japanese Society for Artificial Intelligence. Dr. Goto is a fellow of IEEE and a member of the Engineering Academy of Japan. He has received a number of awards and honors, including Distinguished Achievement Awards from the Institute of Electronics, Information and Communication Engineering, and the same award from Japanese Society of Artificial Intelligence, the best paper award from ICCC and Jubilee Medal from IEEE.

Biography of Claudionor Coelho
Claudionor Coelho obtained his BSEE (summa cum laude) and MSCS from the Federal University of Minas Gerais in Belo Horizonte, Brazil, his PhD-EE/CS from Stanford University, and his MBA from IBMEC.

He has worked in several companies in the US, both in technical and in upper management positions, including Integrated Information Technology and in Verplex Systems, where he directed the BlackTie™ team and was responsible for the development of OVL. He was a founder of several startups, and he is a counselor for FirCapital Partners in startup strategy and technology.

Dr. Coelho has written award-winning papers and books, and was a contributing author to Advanced Formal Verification from Kluwer Academic Publishers. He is currently Associate Professor at the Computer Science Department at the Federal University of Minas Gerais, Brazil.

About Jasper Design Automation
Founded in 1999, Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company headquartered in Mountain View, California. Delivering breakthrough verification completeness, productivity and predictability, the JasperGold® Verification System solution formally verifies that complex design blocks meet their high level requirements, as defined by their specifications, without any testbench development. JasperGold Verification System automatically isolates bugs with a fast, unique debugging capability, trimming crucial months off the verification schedule. For further details on how to improve design quality, verification productivity, debug efficiency and verification reuse, visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, Tempus Quest, JasperGold Verification System and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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