Jasper Design Automation’s JasperGold® System 4.0 Selected As A Finalist In Second Annual DesignVision Awards

Advanced Formal Verification Solution From Jasper Honored A Second Time For Being Among The Most Unique And Beneficial To The Industry

Mountain View, Calif. – February 6, 2006 – Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced that its JasperGold® Verification System, release 4.0, has been named a finalist in the International Engineering Consortium’s Second Annual DesignVision Awards. The DesignVision Awards program recognizes technologies, applications, products, and services judged to be the most unique and beneficial to the electronic design and semiconductor industries. JasperGold, a block-level verification solution that employs state-of-the-art formal verification technology to exhaustively verify RTL blocks without simulation or test vectors, was nominated in the Design Verification Tools category and selected as one of three finalists from among scores of respected candidates.

“JasperGold Verification System was named for the second time as a finalist in the Design Verification Tools category because of its innovative approach to complete verification,” said Craig Cochran, vice president of marketing at Jasper. “JasperGold System 4.0 is the first product to deliver 100% complete verification of block-level design requirements. Our selection as a DesignVision finalist, together with our high level of customer satisfaction, provides strong evidence that JasperGold is breaking new ground in verification completeness and debugging productivity.”

One award will be given for the winning product in each of nine different categories. The first public announcement of the winners will take place before the Tuesday Keynote on February 7th at noon in the Theater of the Santa Clara Convention Center.

“This is our second year of offering the DesignVision Awards program and we have expanded our categories. The finalists in the Design Verification Tools category represent products within the industry that have provided distinctive advances in design verification," said Dr. Barry Sullivan, DesignCon 2006 Program Director. “The IEC is pleased to provide this recognition to companies whose products exemplify our standard of service to the industry."

For details on how to improve design quality, verification productivity, predictability and verification
reuse, please visit: http://www.jasper-da.com.

About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company’s flagship product, JasperGold™ Verification System, is the first verification product to deliver systematic complete verification, and accomplishes this task within predictable, finite schedule constraints. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to achieve complete verification, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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Editorial Contact: Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153 / francine@thinkbold.com