JasperGold Verification System 4.1 Delivers Systematic Formal Verification to the SystemVerilog Community

New Release Supports Full Formal Verification of
SystemVerilog Assertions and Improves Verification Productivity

Mountain View, Calif. – February 22, 2006 – Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced JasperGold® Verification System 4.1, a new release of the company’s flagship formal verification solution. JasperGold System 4.1 includes a robust implementation of the SystemVerilog Assertion (SVA) language for formal verification, significant improvements to the automation of the formal process, and a major increase of new content in Formal Testplanner, Jasper’s knowledgebase of verification IP, strategies and methodology. With industry-leading verification and debugging support for the Property Specification Language (PSL), SVA, OVL, Verilog and VHDL, JasperGold System 4.1 delivers faster, easier, and more complete systematic verification for virtually all hardware design environments.

“Industry-standard assertion languages like SVA are accelerating the adoption of full formal verification solutions among verification teams worldwide,” said Craig Cochran, vice president of marketing at Jasper Design Automation. “JasperGold Verification System’s excellent implementations of SVA and PSL for formal verification help design and verification teams find and remove bugs faster and easier, and ensure absolute correctness where it matters most.”

Robust Formal SVA Implementation
SystemVerilog usage is growing rapidly in North America and Japan. The SVA language is being used primarily in dynamic simulation to improve observability for debugging. By supporting SVA, Jasper provides SystemVerilog simulation users a smooth migration path to systematic formal verification, where they can now target the most critical parts of their designs to ensure correctness to the spec. Jasper’s SVA implementation was developed by the same team which delivered its highly tuned formal support for the property specification language (PSL).

”The formal method is an important component for verifying advanced designs at Sun,” said Catherine Ahlschlager, hardware manager, Formal Technologies Group at Sun Microsystems. “We are working with Jasper to deploy formal verification of SystemVerilog Assertions to prove deep corner cases of our designs.”

Improvements in automation and capacity
JasperGold System 4.1 also includes significant improvements that promote rapid interactive generation of verification constraints, improve push-button verification capacity, and simplify the handling of complex state devices that would otherwise result in extended run times in other tools. These improvements help to improve productivity, capacity and performance in the verification process, resulting in reduced schedules and higher standards of verification completeness.

Expanded Formal Verification IP and Language Support
Formal Testplanner, Jasper’s knowledgebase of verification IP, strategies and methodology, has been enhanced with major new content in support of the new language standards, as well as new chapters on several design types. Formal Testplanner now includes Introductions to PSL and SVA, a formal verification tutorial, and new Parameterizable Property Macros (PPMs), which simplify the creation of powerful high-level properties. Additionally, it contains new chapters on verifying cache controllers, SDR memory controllers, DDR and DDR2 memory controllers, and OCP-IP interface compliance.

Availability
JasperGold Verification System 4.1 is now available.

About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company’s flagship product, JasperGold Verification System, is the first verification product to deliver systematic complete verification, and accomplishes this task within predictable, finite schedule constraints. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to achieve complete verification, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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Editorial Contact: Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153 / francine@thinkbold.com