Jasper Design Automation Names Brian Bailey
As Technical Advisory Board Member

Verification Industry Veteran to Contribute Broad Commercial Verification
Perspective to Jasper Technical Direction

Mountain View, Calif. – February 22, 2006 – Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today named Brian Bailey as the newest member of its Technical Advisory Board (TAB). Brian Bailey is a renowned verification industry veteran and visionary, having contributed to the early development of RTL simulation, hardware emulation, hardware/software co-design and transaction-level modeling using SystemC. He currently chairs the Interface Technical Committee within Accellera, and is also a prolific writer, having published many articles and two recent books on the subject of design and verification. Mr. Bailey replaces Claudionor Coelho on the TAB, who was recently appointed as Jasper’s vice president of engineering.

"Brian Bailey is an ideal addition to our technical advisory board, having contributed greatly to the commercial development of many verification technologies and written many papers and books influencing the direction of the industry," said Kathryn Kranen, president and CEO of Jasper. "His commercial start-up experience, standards leadership and breadth of knowledge of the overall verification space make him a perfect complement to our existing TAB members, and will aid Jasper in leading the adoption of the systematic approach to formal verification."

"Having worked closely with several visionary verification startups, I am very enthusiastic about joining Jasper’s TAB to help move the verification industry to the next level," said Brian Bailey. "With the world moving to highly-leveraged IP reuse-based design flows and platform-based design, systematic formal verification is becoming an imperative. Full formal verification of critical functionality, combined with coverage metrics for the rest of the design, is the best way to ensure correctness where it matters most and enable more aggressive, competitive designs."

Brian Bailey is an industry and management consultant specializing in the functional verification of electronic systems. He has experience implementing verification tools and solutions for companies of all sizes, and has been involved in some of the most significant advances in the field. He has been proclaimed as one of the visionaries of the industry and today spends most of his time helping start-up companies turn their ideas into practical realities. He is active in the standards community, currently chairing the Interface Technical Committee within Accellera, has published two books in 2005 and is a popular contributor to the press and conferences. He graduated from Brunel University in England with a first class honors degree in Electrical and Electronic Engineering.

About Jasper’s Technical Advisory Board
Jasper’s Technical Advisory Board (TAB) is made up of world-renowned visionaries from the academic and commercial world in the field of verification. The TAB’s purpose is to advise Jasper’s management team on research trends in formal verification and verification in general, provide guidance on Jasper’s technical product development, and to educate students and the market on trends in formal verification.

In addition to Brian Bailey, the TAB currently includes Alan Hu, associate head of the Department of Computer Science at the University of British Columbia; Sharad Malik, professor in the Department of Electrical Engineering, Princeton University; and Satoshi Goto, professor at the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan.

About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company’s flagship product, JasperGold® Verification System, is the first verification product to deliver systematic complete verification, and accomplishes this task within predictable, finite schedule constraints. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to achieve complete verification, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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Editorial Contact: Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153 / francine@thinkbold.com