JASPER DESIGN AUTOMATION ENABLES 100% ACTUAL COVERAGE FOR VHDL USERS

JasperGold® Verification System Breakthrough Formal Verification Solution Now Supports VHDL Verification and Debugging


Mountain View, Calif. - March 8, 2005 - Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced that its flagship product, JasperGold Verification System, now supports verification and debugging of designs written in the VHDL language, in addition to Verilog. VHDL is the predominant design language used in Europe, where Jasper is exhibiting for the first time at the Design and Test Conference (DATE) this week in Munich, Germany. By providing verification and debugging support for VHDL, Jasper now enables VHDL users worldwide to break through the coverage barrier and achieve 100% actual coverage in the verification of even their most complex digital designs.

JasperGold Verification System is the first formal verification solution to deliver 100% actual coverage on a complete set of high-level requirements, predictably and within verification schedule constraints. High-level requirements are similar to assertions and are compatible with assertion-based verification (ABV), but they work at a higher level of abstraction, enabling greater design coverage and higher proof of correctness, independent of the implementation. With 10x the capacity of other formal solutions, JasperGold Verification System is unique in its ability to fully prove high-level requirements on designer-sized blocks, ensuring that the most important aspects of a design, derived from the design specification, are verified with 100% actual coverage.

"Having been used successfully in verification and debug of more than 45 production chips written in Verilog, JasperGold Verification System is already changing the way designers think about verification in North America and Japan," said Kathryn Kranen, president and CEO at Jasper. "With support for VHDL, and a very disciplined verification methodology for achieving 100% coverage of blocks as they are being designed, JasperGold Verification System is sure to capture the attention of Europe's leading design teams, renowned for their rigorous design quality."

Availability
VHDL language support is available today within JasperGold Verification System v3.1, at no additional charge to licensees of JasperGold Verification System.

About Jasper Design Automation
Founded in 1999, Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company headquartered in Mountain View, California. The first verification product to deliver 100% actual coverage within predictable, finite schedule constraints, the JasperGold Verification System solution formally verifies that complex design blocks meet their high-level requirements, as defined by their specifications, without any testbench development. JasperGold Verification System automatically isolates bugs with a fast, unique debugging capability, trimming crucial months off the verification schedule. For further details on how to improve design quality, verification productivity, predictability and verification reuse, visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, JasperGold Verification System, PreCognitive Engine, Design Tunneling and Jasper Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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Editorial Contact:
Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153
francine@thinkbold.com