JASPER ANNOUNCES USER-FRIENDLY FORMAL FUNCTIONAL VERIFICATION SOLUTION FOR 100% PROOF OF SPEC-LEVEL REQUIREMENT

PreCognitive Engine Breaks the Capacity Barrier, Eliminates Costly Design Respins

Mountain View, CA - May 19, 2003 - Jasper Design Automation, a privately held company targeting true formal functional verification, today announced JasperGold Verification System™, a complete, user-friendly formal verification solution that can detect all of the design bugs in most complex electronic design blocks. JasperGold Verification System, Jasper's ground-breaking product, was developed to tackle the severe capacity limitations and ease-of-use concerns that have long plagued traditional formal verification tools.

Jasper's PreCognitive Engine™ overcomes the formal verification capacity problem by using State Space Tunneling™ to guide the formal proof engines to analyze only those portions of the design relevant to proving each requirement - without requiring any modification of the design by the user. Relevance Directives™ enable the user to direct the PreCognitive Engine from a high-level point-of-view, much like floor planning guides Place and Route. Past attempts at "true" formal verification have suffered from state space explosion as the number of states to explore increased exponentially with design size until the design was simply too large to verify, even on the largest computers. Attempts by today's formal analysis tool providers to counteract the capacity problem rely upon Bounded Model Checking, Dynamic or Semi-Formal Verification, which limits the state space exploration to a small "proof radius". Relying upon a proof radius sacrifices the goal of 100% proof and fails to expose severe corner case design bugs that reside in the unproven space outside the proof radius. With JasperGold Verification System's PreCognitive Engine, no restrictive proof radius applies, since requirements are proven across the entire design state space. And as an added benefit, users need not possess the PhD-level proficiency required to employ traditional formal verification tools.

In contrast to many other formal verification tools, which operate at the "SuperLint" or assertion level, JasperGold Verification System's PreCognitive Formal Verification™ executes spec-level requirements which are captured either in Verilog or translated from higher-level languages. When executing at the assertion-level with other tools, a user can verify hundreds of assertions for a design block and still not prove that the block meets its functional requirements. By executing at a higher level, JasperGold Verification System enables the user to fully capture the spec-level requirements for a design block and exhaustively verify that the requirements are met. This achieves a level of confidence impossible to reach with assertions alone. Requirements are captured in dramatically fewer lines of RTL than the design block itself, typically one tenth to one hundredth the number of lines. Jasper offers pre-built Jasper Proof Kits™ for a wide variety of standard interfaces, including the newly announced PCI Express Proof Kit™. Today, JasperGold Verification System applies to control logic and datapath-related design blocks that do not undergo data transformation or perform mathematical computations.

"Customers tell us that the only thing growing faster than design verification complexity is the cost of missing a bug, with respins approaching a million dollars", said Kathryn Kranen, newly appointed President and CEO of Jasper Design Automation. "Clearly, the industry has reached an inflection point in which simulating until you run out of time is not enough. With JasperGold Verification System, project teams can be absolutely certain that their design blocks are bug-free with respect to functional requirements."

"Using JasperGold Verification System, we were able to find a problem in a design that we had already taped-out", said Suresh Thirumandas, Director of IC Design at Broadcom. "If we had been able to use it beforehand, we could have saved ourselves an unnecessary respin. Among our customers, the number one concern is how our chips have been verified, so it is a great marketing advantage for Broadcom to be able to state that our designs have been formally verified and proven."

Pricing and Availability

JasperGold Verification System™ is available June 1, 2003, with prices beginning at $225,000. Jasper also offers pre-built Jasper Proof Kits™ for a variety of standard interfaces, such as PCI Express, AGP, DDR, Gigabit Ethernet, PCI, PCI-X, and many more.

About Jasper Design Automation
Jasper Design Automation, formerly Tempus Fugit, was founded in 1999 and is a privately funded Electronic Design Automation (EDA) company with its corporate headquarters located in Mountain View, California. Based on true formal functional verification, the company's breakthrough PreCognitive Formal Verification Technology™ begins at the spec-level to deliver 100% exhaustive design requirement proof for today's ultra complex Integrated Circuits. For further information visit: http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, Tempus Quest, JasperGold Verification System and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.