Jasper Design Automation Unveils Free Tool for Easy Generation of Structured Verification Plans

New GamePlan™ Verification Planner Assists in the Creation and Tracking Of Multiple Verification Approaches By Multiple Teams Within A Single Comprehensive Verification Plan

Mountain View, Calif. – July 19, 2006 – Addressing one of the key problems facing verification teams today, Jasper Design Automation unveiled GamePlan™ Verification Planner, a new tool being offered at no cost that generates and tracks the progress of verification plans. The first of its kind, GamePlan Verification Planner promotes collaboration within multiple verification teams by providing a single, comprehensive structured framework for identifying what design features need to be tested, what verification technologies are required for testing, and for prioritizing and tracking the progress of each feature tested. GamePlan Verification Planner fills the gaps in today’s verification flow by adding a process for systematic verification that can fit into any environment, and that respects all verification methods, including formal verification, simulation and others. By providing GamePlan as a free tool, Jasper Design Automation is enabling systematic usage of formal verification alongside other technologies, and is taking a leading industry role in promoting a structured approach to verification.

“The most successful deployments of formal verification are by customers who integrated it systematically within their simulation-based verification environment,” said Rajeev Ranjan, chief technology officer at Jasper Design Automation. “This powerful deployment of systematic formal underlies Jasper’s rapid growth, and it is what led us to develop GamePlan Verification Planner. By making GamePlan’s technology available for free to all verification engineers, we provide strong support of the industry’s move to formal verification for higher quality and completeness, and accelerate the adoption of high-level systematic formal using the JasperGold Verification System. Users of the new tool will also be gratified to know that GamePlan supports legacy technologies and coverage-based verification methods.”
GamePlan Verification Planner provides a very flexible, intuitive user interface for capturing the main features of a design, the expected functionality, verification approaches, test priorities, technologies required, and test status. The tool generates a verification test matrix to provide an overview-at-a-glance of overall verification status, as well as a comprehensive verification test plan in hyperlinked HTML format. The test matrix and HTML verification test plan can be easily shared over corporate networks to enable collaboration and easy reporting of project status to engineering management. GamePlan’s testplan structure is very customizable and all data is stored in XML for maximum interoperability.

“GamePlan is a great solution to the dreaded ‘blank page syndrome’ as it provides a structure to enable you to easily capture a structured verification plan,” said Brian Bailey, chief technology officer of Poseidon Design Systems and noted verification expert. “The really valuable thing about GamePlan is that it enables you to easily integrate a systematic formal testplan into your overall verification strategy, determining which parts of the system are to be tested using formal, simulation or other methods.”

Sean Smith, chief verification architect at Denali Software, added, “GamePlan provides significant value to large projects that involve collaborative efforts between verification teams. Groups addressing formal and simulation-based efforts can prioritize and coordinate strategies to verify different features of a chip, and then integrate the results into a comprehensive report. Since the results are generated in a clean hyper-linked HTML format, it requires minimal effort to track and report status to engineering management.”

See GamePlan Verification Planner, and attend a free seminar
GamePlan Verification Planner will be demonstrated in the Jasper booth #1628 at the 43rd Design Automation Conference (DAC) in San Francisco, July 24-27, 2006. Jasper Design Automation will also be offering a free seminar on Automating the Creation of Structured Verification Plans using GamePlan in the Jasper suites. To sign up for a seminar, visit http://www.jasper-da.com/events/DAC2006 or visit the Jasper booth at DAC.

Availability
GamePlan Verification Planner will be available for free download from the Jasper Design Automation corporate website within a few weeks after DAC. Check http://www.jasper-da.com/gameplan for details.

About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company’s flagship product, JasperGold Verification System, is the first verification product to deliver complete “deep formal” systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold Express, Jasper’s formal ABV solution, provides the industry’s leading “light formal” solution, complementing simulation-based approaches by accelerating bug hunting and elimination as well as coverage attainment. The JasperGold family automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to ensure guaranteed correctness where it matters most, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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Editorial Contact: Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153 / francine@thinkbold.com