Jasper Design Automation Announces JasperGold® Verification System 4.2 With Powerful New Capabilities For Ensuring Guaranteed Correctness Where it Matters Most

Improvements in Every Step of the Verification Flow Ease Novice User Adoption Experience While Increasing Advanced User Productivity and Schedule Predictability

Mountain View, Calif. – July 19, 2006 – Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced JasperGold® Verification System 4.2, a robust new release of the company’s flagship formal verification solution that dramatically improves both novice and advanced user experience, and also adds support for the SystemVerilog design language. JasperGold System 4.2 delivers user-focused improvements in every step of the verification flow, including planning, prediction, language support, engine performance, visualization and debugging. Both novice users of formal verification, as well as advanced users, will experience easy adoption and usage, high performance and high debugging productivity.

“According to our customers, the previous versions of JasperGold Verification System already featured the best ‘out of the box’ user experience, when compared with other tools. However, the new improvements in release 4.2 make it even easier for novice users to deploy formal, while providing significant productivity gains for the advanced users,” said Craig Cochran, vice president of marketing at Jasper Design Automation. “The design and verification teams using the new tool tell us it is enabling them to find and remove bugs faster and easier, and is ideally-suited for ensuring correctness where it matters most.”

Speeds Bug Detection and Elimination
With the growth of PSL and SVA assertion languages, new static formal debugging paradigms are needed to enable fast isolation of assertion violations. With JasperGold System 4.2, Jasper builds on its historical strength in static formal debugging by introducing Advanced PSL/SVA Debugging. This new feature automatically displays multi-cycle traces of events contributing to assertion failures, and is tightly integrated with Jasper’s patented “Why” feature to probe the assertion and RTL source interactively to isolate the root causes of violations. Very complex sequences in PSL or SVA can be readily viewed at a glance, in a single window, to illuminate the assertion failure. In addition, new Design Visualization features in v4.2 enable users to visualize a schematic view of the cone-of-influence and analysis regions associated with a property in a particular debugging scenario.

Drives Critical Proofs
JasperGold System 4.2 also includes an advanced new verification engine which seamlessly provides very high verification performance – up to 30 times faster than previous versions on some properties. The new engine has already resulted in several completed proofs on customer designs in which competitive solutions were not able to achieve a completed verification run.

Delivers Better Verification Predictability
JasperGold System 4.2 includes a new feature called “Formal Predictor”, which analyzes a design prior to verification and provides a detailed report on the design’s complexity. This feature enables the user to see, in advance, what areas of the design present complexity for the formal engines, so they can decide where to apply abstractions safely, using JasperGold, to simplify the verification run without sacrificing accuracy or correctness.

Availability
JasperGold Verification System 4.2 is currently available

See JasperGold Verification System 4.2 at DAC
To learn more about JasperGold Verification System 4.2, or to view a demo, please visit Jasper in booth #1628 at the 43rd Annual Design Automation Conference in San Francisco, California at the Moscone Convention Center from July 24th to the 27th. To book time with Jasper’s formal verification experts, or to attend a seminar, please visit: http://www.jasper-da.com/events/DAC2006/index.htm.

About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company’s flagship product, JasperGold Verification System, is the first verification product to deliver complete “deep formal” systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold Express, Jasper’s formal ABV solution, provides the industry’s leading “light formal” solution, complementing simulation-based approaches by accelerating bug hunting and elimination as well as coverage attainment. The JasperGold family automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to ensure guaranteed correctness where it matters most, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.

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Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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Editorial Contact: Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153 / francine@thinkbold.com