| Jasper
Design Automation Hosts First Coverage Interoperability
Forum to Proactively Address Interoperability Of Heterogeneous
Verification Tools
Initiative’s Strong
Momentum Leads to Formation of Accellera Unified Coverage
Interoperability Technical Subcommittee
Mountain
View, Calif. – December 14, 2006 –
Jasper Design Automation, provider of breakthrough high-level
formal verification solutions, today announced it served
as the host company to the first Coverage Interoperability
Forum (CIF) in October 2006. More than 2 dozen highly-respected
industry-leading EDA users and EDA vendors gathered in
a united front of cooperation to proactively address the
issue of interoperability of heterogeneous verification
tools and their respective handling of coverage data.
Formed to be agnostic of any particular coverage methodology
or tool, the Coverage Interoperability Forum addressed
baseline coverage interoperability in order to create
a standard for aggregating and utilizing heterogeneous
coverage information. Based on the success and momentum
created by the forum, the Accellera organization voted
to form a new committee – the Unified Coverage Interoperability
Technical Subcommittee (UCI-TSC) – to address this
standardization effort. This new technical subcommittee
was also announced by Accellera today.
Participants
of the first Coverage Interoperability Forum included
representatives of AMD, Cadence Design Systems, Denali,
D.E. Shaw, Freescale, Hewlett Packard, IBM, Jasper Design
Automation, Nokia, Novas Software, NVIDIA, Poseidon Design
Systems, Real Intent, Sony, Sun Microsystems, Texas Instruments,
and Verification Central. Presentations given by various
participants may be viewed or downloaded at http://www.jasper-da.com/CoverageForum/.
“During
the Coverage Interoperability Forum, we determined that
the first order of business is to begin to identify baseline
coverage interoperability requirements,” said Rajeev
Ranjan, Jasper CTO, responsible for germinating interest
in CIF from the user and EDA communities. “While
it is clearly understood that there is no quick-fix solution,
the clear need coming from the EDA user community supports
such an effort. We have made early inroads into defining
baseline coverage interoperability requirements to deal
with verification data generation, aggregation, analysis,
and metrics, and now these efforts will continue within
the UCI-TSC as part of Accellera. Given that end-users
want to seamlessly combine information from different
tools and that these same customers are developing home
grown solutions today to achieve that goal, the time is
right for this initiative and the Accellera subcommittee
that resulted from it.”
The
Steering Committee of the CIF included Mercedes Tan from
SUN Microsystems, Somdipta Basu from TI, Brian Bailey
from Poseidon, Andrew Piziali from Cadence, Sean Smith
from Denali Software, George Bakewell from Novas, Rajeev
Ranjan from Jasper Design Automation, with David Lacey
of Hewlett-Packard serving as chair.
Jasper
Design Automation Joins Accellera
With the formation of the Coverage Interoperability Technical
Subcommittee within Accellera, Jasper Design Automation
has joined the organization in order to continue to contribute
its expertise in formal coverage to the requirements and
formation of the standard.
About
Jasper Design Automation
Jasper Design Automation is a privately-held Electronic
Design Automation (EDA) company delivering full-formal
IC verification as a competitive advantage for its customers.
Flagship product, JasperGold® Verification System,
is the first to deliver complete “deep formal”
systematic verification, ensuring correctness where it
matters most. Without needing any testbench development,
JasperGold formally verifies that complex IC design blocks
meet high-level requirements defined in their specifications,
and also pre-verifies IP blocks for all usage modes. Jasper’s
formal ABV solution, JasperGold® Express, provides
the industry’s leading “light formal”
solution. It complements simulation-based approaches by
accelerating bug hunting and elimination, as well as coverage
attainment. The JasperGold family automatically isolates
bugs with a fast, unique debugging capability. By isolating
bugs earlier than simulation or formal-assisted simulation
tools, and then proving the absence of bugs, JasperGold
trims crucial months off design schedules. To ensure guaranteed
correctness where it matters most, and improve verification
productivity, predictability and verification reuse, visit
http://www.jasper-da.com.
# # # Jasper
Design Automation, the Jasper Design Automation logo,
JasperGold and Formal Testplanner are trademarks of Jasper
Design Automation, Inc. All other names mentioned are
trademarks, registered trademarks, or service marks of
their respective companies.
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Editorial Contact: Francine Bacchini
ThinkBold Corporate Communications, LLC
+1.408.839.8153 / francine@thinkbold.com
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