Ever-increasing complexity and competitive time-to-market requirements of modern SoCs have placed mounting pressure on designers to improve their productivity and deliver higher quality designs.
Pushing bug-finding responsibility to the verification team dictates that most bugs will not be found until a critical mass of RTL (usually from multiple designers) and testbench code (developed by the verification engineer) has been integrated and debugged. Unfortunately, longer the lifespan of a bug, more costly are its ripple effects.
Given that traditional design and reuse solutions do not provide the essential design visibility necessary to ensure bug-free designs, costly and time-consuming design re-spins occur.
Jasper’s ActiveDesign™ drives higher RTL design quality and designer productivity, reduces verification time, accelerates knowledge transfer, improves design maintenance, and enables efficient design reuse. It delivers early RTL design for debug and verification, as well as enables exploration and reuse of legacy designs and commercial IP. ActiveDesign uses formal analysis, coupled with Jasper's patented Visualize™ technology, to automatically produce interesting waveforms from the (partially-coded) RTL. This is accomplished without the development of a testbench or any input stimulus.
ActiveDesign’s Behavioral Indexing™ technology lets engineers design, concurrently modify, and verify RTL code, then store it in a persistent database containing both the RTL itself and an “index” of its elastic behaviors.
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