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Jasper Design Automation: JasperGold

JasperGold® Verification Family

Formal Verification Unleashed!

OVERVIEW
Jasper formal verification technology delivers compelling benefits throughout the entire SoC design flow, from RTL debug through verification and regression test to post-silicon debug. JasperGold Verification System provides rapid bug detection and debug as well as end-to-end full proofs of expected design behavior. Its powerful analysis capabilities and ease of use make it ideal for early-stage bug hunting as well as ensuring the highest confidence possible in your design functionality via end-to-end full proof.

BENEFITS

Provides highest verification ROI through low effort / high quality exhaustive verification
Dramatically reduces risk of bug escapes and design respins
Greatly improves verification productivity
Provides strongest verification assurance for aggressive design schedules

FEATURES

The only formal verification solution capable of exhaustively verifying block-level end-to-end High-Level Requirements (HLRs)
Unique Design Tunneling!" infrastructure enables advanced proof verification
Multiple parallelized formal engines for maximum verification
Fast, easy and complete verification using predefined 'plug-and-play' formal Proof Accelerator verification components
Sophisticated built-in formal debugging capability

'DEEP FORMAL' VERIFIES COMPLEX END-TO-END PROPERTIES
With Jasper's unique Design Tunneling formal infrastructure, JasperGold Verification System provides the highest level of deep formal productivity available. Properties can be specified as end-to-end block-level microarchitecture statements known as High-Level Requirements. These properties express input-to-output block-level design intent. Proving properties at these higher levels of abstraction is far more powerful and efficient than writing and testing hundreds of lower-level, individual ABV assertions scattered throughout the logic. JasperGold Verification System consistently performs full proofs on properties where other formal tools fail to converge, with an average of 10x proof capacity advantage over the competition.

ACCELERATE YOUR PROOFS!
Jasper's family of Proof Accelerators are included with JasperGold Verification System. These easy-to-use modeling components speed up formal proofs to significantly reduce the complexity of the verification.

JasperGold highest level of deep formal productivity

Deep Formal High-Level Requirements

Formal Testplanner

Often users can simply drop these models into their design to get proofs to converge. They can also be used together with Design Tunneling to converge on an exhaustive solution that would otherwise be unobtainable. Models include such components as:

Datapath modeling
Scoreboarding
FIFOs ... and more!

EXPECT MORE FROM YOUR FORMAL
Today's challenging verification schedules demand correctness, clarity, confidence and closure. Formal verification is a powerful tool for detecting bugs early in the design flow, ensuring the RTL completely meets the specification, regression test and post-silicon debug.

JasperGold Verification System provides the only formal analysis solution available today with end-to-end exhaustive proofs of High-Level Requirements. Rapid bug detection and conclusive bug elimination are the keys to fast, high quality verification.