Structural Property Synthesis App
Ever-increasing complexity and competitive time-to-market requirements of modern SoCs have placed mounting pressure on designers to improve their productivity and deliver higher quality designs. Pushing bug-finding responsibility to the verification team dictates that most bugs will not be found until a critical mass of RTL (usually from multiple designers) and testbench code (developed by the verification engineer) has been integrated and debugged. Unfortunately, the longer the lifespan of a bug, the more costly are its ripple effects. Given that traditional design and reuse solutions do not provide the essential design visibility necessary to ensure bug-free designs, costly and time-consuming design re-spins occur.
The JasperGold® Structural Property Synthesis (SPS) App is used early in the validation process without the need to write a testbench or provide any stimuli. The structural properties are extracted from the RTL semantics and are used in early RTL development as well as RTL sign-off. These structural properties can be configured from a wide variety of predefined functional checks such as dead code checks, finite state machine (FSM) checks, arithmetic overflow checks, etc. The JasperGold SPS App is tightly integrated with the entire set of JasperGold Apps drastically reducing the amount of checks that go undetected, unproven, and undiagnosed. Properties can be ranked, pre-classified and output in standard SystemVerilog Assertions (SVA) which can then be used in any assertion-based verification (ABV) flow such as simulation, formal analysis or emulation to increase functional coverage and reduce debug time. The JasperGold SPS App provides a fully automated flow to identify and generate checks without the need to annotate the RTL.
Structural Property Synthesis automatically generates assertions, constraints, and covers from RTL.
The SPS App helps eliminate common functional design errors and makes sure the code is clean before validation starts. The structural properties are extracted from the RTL semantics and are used for early RTL development as well as RTL sign-off. The SPS App reduces the need to create assertions manually and helps engineers learn about assertions. Designers can use it in conjunction with the JasperGold RTL Development App to study and explore design functionality fast for new or existing designs. Design and verification engineers can use it with the JasperGold Formal Property Verification App to find design errors before simulation is available.
The SPS App increases engineering productivity, improves design quality, and shortens the overall schedule so that the focus can be shifted to other important verification tasks rather than spending time on manually creating these assertions from scratch. It consequently accelerates the adoption of assertion-based verification.