JasperGold: Control & Status Register App
Control & Status Register Verification
A modern SoC has a large number of Control and Status (CS) registers -- even small IP blocks can have hundred(s) of such registers. Writing testbenches to verify even the most basic read/write behaviors is a time-consuming chore that doesn’t scale easily. While some people may think it is straightforward to verify read operations and write operations to a CS register, the verification complexity increases exponentially when advanced features are used, such as register aliasing, bit masks and byte enable, concurrent HW and SW accesses, access latencies, register remapping according to operation modes, protected vs. unprotected transactions, locking conditions, modified write semantic, and read actions.
What is needed is:
- A methodology for capturing formal CS register R/W specifications;
- Solutions that can automatically generate properties form such specifications; and
- A process for exhaustively validating and verifying the correctness of all possible sequences of RD/WRs in any order, as well as all CS register addresses, aliases, and interferences.
The Jasper Solution
The JasperGold® Control & Status Register App allows the specifications of control and status (CS) register configurations and behavioral descriptions in open, familiar formats – either Excel and OpenOffice spreadsheets, common-separated values (CSV) files, or an IP-XACT xml -- without the need to know or learn SVA. In a matter of hours, the App then automatically generates register checks from the definition table, and proceeds to exhaustively verify that the RTL implementation of the registers behaves as specified. Hence, this App enables any engineer to find deep bugs weeks and months sooner than simulation-based flows can.
Additionally, the App is enhanced with a customized GUI for results analysis, featuring Jasper’s unique Visualize™ and QuietTrace™ technologies to expedite debug using absolute minimum length waveforms to show the erroneous behaviors.
- Create and edit register specification in open, human and machine readable Excel/OpenOffice spreadsheets, comma-separated-values (CSV) files, or IP-XACT xml files
- Automatically generate properties WITHOUT the need to learn SVA
- Use the customized GUI for results analysis, featuring Jasper’s unique Visualize™ and QuietTrace™ technologies
- Enable productivity and throughput by allowing multiple proofs to be kicked off in parallel with ProofGrid™ while proof jobs can be managed and tracked using ProofGrid Manager™ in a regression mode
- Note: If you are already capturing your DUT and registers in IP-XACT, we are partnered with Duolog Technologies, (www.duolog.com), a company that specializes in IP-XACT-related specification and data management tools. Highlights of this integration are outlined in this 5 minute video: http://youtu.be/ItzxdJ_FshM
- The JasperGold® Control & Status Register Verification App takes a "formal first" approach, meaning the properties and subsequent verification is truly exhaustive vs. simulation-based approaches.
- The App allows the capture of register specifications in familiar textual formats. No knowledge of SVA is needed, saving significant time and effort.
- The App automatically generates properties capturing the complex semantic related to register interactions, latencies, and read/write semantics, designed such that the user does NOT need to learn formal or SVA.
- The properties the tool automatically generates are optimized for formal, providing faster wall clock run time and better proof performance.
- When used in concert with Jasper’s Visualize™ and QuietTrace™ technologies, debug is significantly easier and faster.