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JasperGold
Verification System Family
The First Verification Solution to Ensure Correctness Where it Matters Most |
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INFORMAL DESIGN ANALYST SIMPLIFIES DESIGNER SANDBOX TESTING
Designers can now run sandbox testing of their RTL code statically, without the time and effort required to build throw away simulation environments. Without any knowledge of formal verification, designers can easily load their RTL into JasperGold or JasperGold Express Verification Systems and launch the InFormal Design Analyst. This unique
analysis environment leverages Jasper’s powerful interactive debugging technology to provide easy, on-the-fly waveform-manipulation controls for the
designer to demonstrate the behavior of their RTL prior to verification hand off. Designers can check logic behavior, examine scenarios of interest, identify potential RTL limitations and constraints, and gain confidence about their code in a matter of minutes, without a testbench. No other solution makes formal sandbox testing as easy and convenient for the designer.
READY-TO-USE FORMAL METHODOLOGY AND VERIFICATION IP
Both JasperGold and JasperGold Express Verification Systems work with Formal Testplanner™, Jasper’s knowledgebase of design-specific methodology tips and example source code for High-Level Requirements. Formal Testplanner jumpstarts the proof process and provides new users with abundant examples and tutorials from which they can learn and gain proficiency. The verification model templates cover numerous design categories including arbitration, memory controllers, and standard protocol interface proof kits. These models can be used directly by the engineer to verify standard components or modified to fit the needs of a custom design block. Combining the methodology of Formal Testplanner with multiple exhaustive proof engines gives JasperGold Verification System the unprecedented ability to provide complete systematic verification across the toughest verification challenges.
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Figure 3: INFORMAL DESIGN ANALYST |
JasperGold Verification Family Key Features
- Seamless scalability from formal ABV through end-to-end block-level full proof
- Multiple parallelized formal engines for maximum verification performance and flexibility
- The only formal verification solution capable of exhaustively verifying
block-level end-to-end High-Level Requirements (HLRs)
- Fast, easy and complete verification using predefined `plug-and-play’ formal verification components
- Pre-emptive notification of complex logic using Formal Predictor™Industry’s strongest PSL and SVA support for formal verification
- The only user-guided designer-level formal sandbox verification infrastructure
- Unique Design Tunneling infrastructure providing interactive feedback for advanced proof verification
- Sophisticated built-in formal debugging capability and interfaces to Novas suite of debugging tools |
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